MT9074AL Zarlink Semiconductor, Inc., MT9074AL Datasheet - Page 68

• Manufacturer Part Number: MT9074AL
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Zarlink Semiconductor, Inc.

MT9074
68
Bit
7
6
5
4
3
2
Table 75 - Per Time Slot Control Words
TXMSG
Name
RTST
RTSL
TTST
LTSL
PCI
(Pages 7 and 8) (T1)
Transmit Message Mode. If high,
the data contained in the Transmit
Message Register (address 18H,
page 1) is transmitted in the
corresponding DS1 time slot. If
zero,
transmitted on the corresponding
DS1 time slot.
Per Channel Inversion. When set
high the data for this channel
sourced from DSTi is inverted
before being transmit onto the
equivalent DS1 channel; the data
received from the incoming DS1
channel
emerges from DSTo.
Remote Time Slot Loopback. If
one,
receive time slot is looped to the
corresponding DS1 transmit time
slot. This received time slot will
also be present on DSTo. If zero,
the loopback is disabled.
Local Time Slot Loopback. If
one, the corresponding transmit
time
corresponding receive time slot.
This transmit time slot will also be
present on the transmit DS1
stream. If zero, this loopback is
disabled.
Transmit Test. If one, a test
signal, either digital milliwatt (when
control bit ADSEQ is one) or
PRBS (Z
will
corresponding DS1 time slot. More
than
activated at once. If zero, the test
signal will not be connected to the
corresponding time slot.
Receive
corresponding DSTo time slot will
be used for testing. If control bit
ADSEQ is one, a digital milliwatt
signal will be transmitted into the
DSTo channel. If ADSEQ is zero,
the
connected to the PRBS (2
detector.
Functional Description
receive
be
one
slot
the
the
15
is
Test.
-1) (ADSEQ is zero),
transmitted
time
corresponding
is
data
inverted
channel
looped
slot
If
on
one,
before
DSTi
may
will
in
to
15
DS1
- 1)
the
the
the
be
be
is
it
Bit
1
0
Table 75 - Per Time Slot Control Words
RPSIG
Name
CC
(Pages 7 and 8) (T1)
Serial Signaling Enable. If set
low, the transmit signaling buffer
for the equivalent DS1 channel will
be sourced from the ST-BUS
channel on CSTi associated with
it. If set high the transmit signaling
RAM must be programmed via the
microport.
Clear Channel. When set high no
robbed bit signaling is inserted in
the
channel. When set low robbed bit
signaling is included in every 6th
channel.
Functional Description
equivalent
Data Sheet
transmit
DS1