IDT72V36110L7-5PF IDT, Integrated Device Technology Inc, IDT72V36110L7-5PF Datasheet - Page 17
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IDT72V36110L7-5PF
Manufacturer Part Number
IDT72V36110L7-5PF
Description
IC FIFO 131KX36 7-5NS 128QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V36110L7-5BB.pdf
(48 pages)
Specifications of IDT72V36110L7-5PF
Function
Synchronous
Memory Size
4.7M (131K x 36)
Data Rate
166MHz
Access Time
5ns
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Configuration
Dual
Density
4.5Mb
Access Time (max)
5ns
Word Size
36b
Organization
128Kx36
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
133.3MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.15V
Operating Supply Voltage (max)
3.45V
Supply Current
40mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
128
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V36110L7-5PF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V36110L7-5PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V36110L7-5PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V36110L7-5PFI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
65,536 x 36 and 131,072 x 36
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
3rd Parallel Offset Write/Read Cycle
4th Parallel Offset Write/Read Cycle
D/Q8
D/Q8
D/Q8
D/Q8
16
16
8
8
IDT72V36100 ⎯
EMPTY OFFSET REGISTER (PAE)
EMPTY OFFSET REGISTER (PAE)
FULL OFFSET REGISTER (PAF)
FULL OFFSET REGISTER (PAF)
15
15
7
7
14
14
6
6
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
13
13
5
5
x9 Bus Width
12
12
4
4
11
11
3
3
10
10
2
2
TM
D/Q0
D/Q0
D/Q0
D/Q0
36-BIT FIFO
1
9
1
9
17
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
6th Parallel Offset Write/Read Cycle
3rd Parallel Offset Write/Read Cycle
4th Parallel Offset Write/Read Cycle
5th Parallel Offset Write/Read Cycle
D/Q8
D/Q8
D/Q8
D/Q8
D/Q8
D/Q8
16
16
8
8
IDT72V36110 ⎯
EMPTY OFFSET REGISTER (PAE)
EMPTY OFFSET REGISTER (PAE)
EMPTY OFFSET REGISTER (PAE)
FULL OFFSET REGISTER (PAF)
FULL OFFSET REGISTER (PAF)
FULL OFFSET REGISTER (PAF)
15
15
7
7
14
14
6
6
13
13
5
5
COMMERCIAL AND INDUSTRIAL
# of Bits Used:
16 bits for the IDT72V36100
17 bits for the IDT72V36110
Note: All unused bits of the
LSB & MSB are don’t care
x9 Bus Width
12
12
4
4
TEMPERATURE RANGES
11
11
3
3
OCTOBER 22, 2008
10
10
2
2
6117 drw07a
D/Q0
D/Q0
D/Q0
D/Q0
D/Q0
D/Q0
17
17
1
1
9
9