IDT72V36110L7-5PF IDT, Integrated Device Technology Inc, IDT72V36110L7-5PF Datasheet - Page 22
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IDT72V36110L7-5PF
Manufacturer Part Number
IDT72V36110L7-5PF
Description
IC FIFO 131KX36 7-5NS 128QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V36110L7-5BB.pdf
(48 pages)
Specifications of IDT72V36110L7-5PF
Function
Synchronous
Memory Size
4.7M (131K x 36)
Data Rate
166MHz
Access Time
5ns
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Configuration
Dual
Density
4.5Mb
Access Time (max)
5ns
Word Size
36b
Organization
128Kx36
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
133.3MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.15V
Operating Supply Voltage (max)
3.45V
Supply Current
40mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
128
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V36110L7-5PF
Available stocks
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Part Number
Manufacturer
Quantity
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Company:
Part Number:
IDT72V36110L7-5PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
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Part Number:
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Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
BUS-MATCHING (BM, IW, OW)
During Master Reset, the state of these pins is used to configure the device bus
sizes. See Table 1 for control settings. All flags will operate on the word/byte
size boundary as defined by the selection of bus width. See Figure 4 for Bus-
Matching Byte Arrangement.
BIG-ENDIAN/LITTLE-ENDIAN ( BE )
HIGH on BE during Master Reset will select Little-Endian format. This function
is useful when the following input to output bus widths are implemented: x36 to
x18, x36 to x9, x18 to x36 and x9 to x36. If Big-Endian mode is selected, then
the most significant byte (word) of the long word written into the FIFO will be read
out of the FIFO first, followed by the least significant byte. If Little-Endian format
is selected, then the least significant byte of the long word written into the FIFO
will be read out first, followed by the most significant byte. The mode desired is
configured during master reset by the state of the Big-Endian (BE) pin. See
Figure 4 for Bus-Matching Byte Arrangement.
PROGRAMMABLE FLAG MODE (PFM)
mable flag timing mode. A HIGH on PFM will select Synchronous Programmable
flag timing mode. If asynchronous PAF/PAE configuration is selected (PFM,
LOW during MRS), the PAE is asserted LOW on the LOW-to-HIGH transition
of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of WCLK.
Similarly, the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK.
MRS) , the PAE is asserted and updated on the rising edge of RCLK only and
not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK
only and not RCLK. The mode desired is configured during master reset by the
state of the Programmable Flag Mode (PFM) pin.
INTERSPERSED PARITY (IP)
A HIGH will select Interspersed Parity mode. The IP bit function allows the user
to select the parity bit in the word loaded into the parallel port (D
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bits are located in bit position D
D
Parity mode is selected, then D
and D
Reset by the state of the IP input pin. Interspersed Parity control only has an
effect during parallel programming of the offset registers. It does not effect the data
written to and read from the FIFO.
OUTPUTS:
FULL FLAG ( FF/IR )
is selected. When the FIFO is full, FF will go LOW, inhibiting further write
operations. When FF is HIGH, the FIFO is not full. If no reads are performed
after a reset (either MRS or PRS), FF will go LOW after D writes to the FIFO
(D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110). See
Figure 7, Write Cycle and Full Flag Timing (IDT Standard Mode), for the
relevant timing information.
when memory space is available for writing in data. When there is no longer
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
65,536 x 36 and 131,072 x 36
35
If synchronous PAE/PAF configuration is selected (PFM, HIGH during
During Master Reset, a LOW on IP will select Non-Interspersed Parity mode.
The pins BM, IW and OW are used to define the input and output bus widths.
During Master Reset, a LOW on BE will select Big-Endian operation. A
During Master Reset, a LOW on PFM will select Asynchronous Program-
This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF) function
In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW
during the parallel programming of the flag offsets. If Non-Interspersed
32
, D
33
, D
34
and D
35
are ignored. IP mode is selected during Master
8
, D
17
and D
28
are is assumed to be valid bits
8
, D
0
TM
17
-Dn) when
36-BIT FIFO
, D
26
and
22
any free space left, IR goes HIGH, inhibiting further write operations. If no reads
are performed after a reset (either MRS or PRS), IR will go HIGH after D writes
to the FIFO (D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110).
See Figure 9, Write Timing (FWFT Mode), for the relevant timing information.
counts the presence of a word in the output register. Thus, in FWFT mode, the
total number of writes necessary to deassert IR is one greater than needed to
assert FF in IDT Standard mode.
double register-buffered outputs.
EMPTY FLAG ( EF/OR )
function is selected. When the FIFO is empty, EF will go LOW, inhibiting further
read operations. When EF is HIGH, the FIFO is not empty. See Figure 8, Read
Cycle, Empty Flag and First Word Latency Timing (IDT Standard Mode), for
the relevant timing information.
at the same time that the first word written to an empty FIFO appears valid on
the outputs. OR stays LOW after the RCLK LOW to HIGH transition that shifts
the last word from the FIFO memory to the outputs. OR goes HIGH only with
a true read (RCLK with REN = LOW). The previous data stays at the outputs,
indicating the last word was read. Further data reads are inhibited until OR goes
LOW again. See Figure 10, Read Timing (FWFT Mode), for the relevant timing
information.
mode, OR is a triple register-buffered output.
PROGRAMMABLE ALMOST-FULL FLAG ( PAF )
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (MRS), PAF will go LOW after (D - m) words are written
to the FIFO. The PAF will go LOW after (65,536-m) writes for the IDT72V36100
and (131,072-m) writes for the IDT72V36110. The offset “m” is the full offset
value. The default setting for this value is stated in the footnote of Table 1.
IDT72V36100 and (131,073-m) writes for the IDT72V36110, where m is the
full offset value. The default setting for this value is stated in Table 2.
Standard and FWFT Mode), for the relevant timing information.
on the LOW-to-HIGH transition of the Write Clock (WCLK). PAF is reset to HIGH
on the LOW-to-HIGH transition of the Read Clock (RCLK). If synchronous PAF
configuration is selected, the PAF is updated on the rising edge of WCLK. See
Figure 20, Asynchronous Almost-Full Flag Timing (IDT Standard and FWFT
Mode).
PROGRAMMABLE ALMOST-EMPTY FLAG ( PAE )
reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW
when there are n words or less in the FIFO. The offset “n” is the empty offset
value. The default setting for this value is stated in the footnote of Table 1.
in the FIFO. The default setting for this value is stated in Table 2.
(IDT Standard and FWFT Mode), for the relevant timing information.
In IDT Standard mode, EF is a double register-buffered output. In FWFT
In FWFT mode, the PAF will go LOW after (65,537-m) writes for the
See Figure 18, Synchronous Programmable Almost-Full Flag Timing (IDT
See Figure 19, Synchronous Programmable Almost-Empty Flag Timing
The IR status not only measures the contents of the FIFO memory, but also
FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (EF)
In FWFT mode, the Output Ready (OR) function is selected. OR goes LOW
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
If asynchronous PAF configuration is selected, the PAF is asserted LOW
The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO
In FWFT mode, the PAE will go LOW when there are n+1 words or less
EF/OR is synchronous and updated on the rising edge of RCLK.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008