AD5516-1 Analog Devices, AD5516-1 Datasheet - Page 3

• Manufacturer Part Number: AD5516-1
• Description: 16-Channel/ 12-Bit Voltage-Output DAC with 14-Bit Increment Mode
• Manufacturer: Analog Devices

AC CHARACTERISTICS
Parameter
Output Voltage Settling Time (Mode 1)
Output Voltage Settling Time (Mode 2)
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Crosstalk
Analog Crosstalk AD5516-1
Digital Feedthrough
Output Noise Spectral Density @ 1 kHz
NOTES
1
2
3
4
Specifications subject to change without notice.
TIMING CHARACTERISTICS
Parameter
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
4
Specifications subject to change without notice.
See Terminology section.
Guaranteed by design and characterization; not production tested.
A version: Industrial temperature range –40°C to +85°C.
UPDATE1
UPDATE2
CLKIN
1
2
3
4
5
6
7
7MODE2
8MODE1
9MODE2
10
12
See Timing Diagrams in Figures 1 and 2.
Guaranteed by design and characterization; not production tested.
All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
This is measured with the load circuit of Figure 3.
Timed from the end of a write sequence.
11
4
1, 2
1, 2, 3
Limit at T
(A Version)
32
750
20
20
20
15
5
5
0
10
400
10
200
10
20
20
MIN
(V
= DACGND = 0 V; REF_IN = 3 V; All outputs unloaded. All specifications T
, T
DD
MAX
= +4.75 V to +13.2 V, V
4
4
(V
AGND = DGND = DACGND = 0 V. All specifications T
DD
Unit
kHz max
kHz max
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
= +4.75 V to +13.2 V, V
1
A Version
32
2.5
0.85
5
10
1
150
CC
) and timed from a voltage level of (V
SS
Conditions/Comments
DAC Update Rate (Mode 1)
DAC Update Rate (Mode 2)
SCLK Frequency
SCLK High Pulsewidth
SCLK Low Pulsewidth
SYNC Falling Edge to SCLK Falling Edge Setup Time
D
D
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time (Standalone Mode)
Minimum SYNC High Time (Daisy-Chain Mode)
BUSY Rising Edge to SYNC Falling Edge
18th SCLK Falling Edge to SYNC Falling Edge (Standalone Mode)
SYNC Rising Edge to SCLK Rising Edge (Daisy-Chain Mode)
SCLK Rising Edge to D
RESET Pulsewidth
= –4.75 V to –13.2 V; AV
3
IN
IN
Setup Time
Hold Time
nV-s typ
Unit
V/ s typ
nV-s typ
nV-s typ
nV-s typ
nV/(Hz)
SS
s max
s max
= – 4.75 V to –13.2 V; AV
1/2
typ
CC
OUT
= 4.75 V to 5.25 V; DV
1 LSB Change around Major Carry
Conditions/Comments
100 pF, 5 kΩ Load Full-Scale Change
100 pF, 5 kΩ Load, 1 Code Increment
AD5516-1
IL
Valid (Daisy-Chain Mode)
+ V
MIN
IH
to T
CC
)/2.
= 4.75 V to 5.25 V; DV
MAX
unless otherwise noted.)
MIN
CC
to T
= 2.7 V to 5.25 V; AGND = DGND
MAX
unless otherwise noted.)
CC
= 2.7 V to 5.25 V;
AD5516