LTC2410 Linear Technology, LTC2410 Datasheet - Page 10

• Manufacturer Part Number: LTC2410
• Description: 24-Bit No Latency ADC with Differential Input and Differential Reference
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
LTC2410
on the rising edge of the 32nd SCK pulse. On the falling
edge of the 32nd SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the IN
within the – 0.3V to (V
operating range, a conversion result is generated for any
differential input voltage V
+FS = 0.5 • V
+FS, the conversion result is clamped to the value corre-
sponding to the +FS + 1LSB. For differential input voltages
below –FS, the conversion result is clamped to the value
corresponding to –FS – 1LSB.
10
Table 2. LTC2410 Output Data Format
Differential Input Voltage
V
V
0.5 • V
0.25 • V
0.25 • V
0
–1LSB
– 0.25 • V
– 0.25 • V
– 0.5 • V
V
*The differential input voltage V
**The differential reference voltage V
IN
IN
IN
* 0.5 • V
* < –0.5 • V
*
REF
SDO
REF
SCK
CS
REF
REF
REF
. For differential input voltages greater than
REF
REF
** – 1LSB
**
** – 1LSB
**
**
** – 1LSB
REF
U
Hi-Z
REF
SLEEP
**
**
CC
U
BIT 31
IN
EOC
+ 0.3V) absolute maximum
from –FS = –0.5 • V
+
1
and IN
IN
BIT 30
= IN
“0”
W
Bit 31
EOC
REF
–
0
0
0
0
0
0
0
0
0
0
+
pins is maintained
– IN
2
= REF
–
.
BIT 29
+
Bit 30
SIG
DMY
– REF
Figure 3. Output Data Timing
0
0
0
0
0
0
0
0
0
0
U
3
–
.
REF
BIT 28
MSB
Bit 29
SIG
1
1
1
1
1
0
0
0
0
0
to
4
DATA OUTPUT
BIT 27
Bit 28
Frequency Rejection Selection (F
The LTC2410 internal oscillator provides better than 110dB
normal mode rejection at the line frequency and all its
harmonics for 50Hz 2% or 60Hz 2%. For 60Hz rejec-
tion, F
rejection the F
The selection of 50Hz or 60Hz rejection can also be made
by driving F
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
MSB
1
0
0
0
0
1
1
1
1
0
5
O
Bit 27
should be connected to GND while for 50Hz
0
1
1
0
0
1
1
0
0
1
26
O
O
to an appropriate logic level. A selection
pin should be connected to V
Bit 26
LSB
BIT 5
0
1
0
1
0
1
0
1
0
1
24
27
Bit 25
BIT 0
0
1
0
1
0
1
0
1
0
1
32
…
…
…
…
…
…
…
…
…
…
…
CONVERSION
O
)
2410 F03
Bit 0
0
1
0
1
0
1
0
1
0
1
CC
.