LTC2410 Linear Technology, LTC2410 Datasheet - Page 7

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LTC2410

Manufacturer Part Number
LTC2410
Description
24-Bit No Latency ADC with Differential Input and Differential Reference
Manufacturer
Linear Technology
Datasheet

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FU CTIO AL BLOCK DIAGRA
TEST CIRCUITS
APPLICATIO S I FOR ATIO
CONVERTER OPERATION
Converter Operation Cycle
The LTC2410 is a low power, delta-sigma analog-to-
digital converter with an easy to use 3-wire serial interface.
Its operation is made up of three states. The converter
operating cycle begins with the conversion, followed by
the low power sleep state and ends with the data output
(see Figure 1). The 3-wire interface consists of serial data
output (SDO), serial clock (SCK) and chip select (CS).
Initially, the LTC2410 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
While in this sleep state, power consumption is reduced by
an order of magnitude. The part remains in the sleep state
as long as CS is HIGH. The conversion result is held
indefinitely in a static shift register while the converter is
in the sleep state.
REF
REF
GND
V
IN
IN
CC
+
+
U
+
U
SDO
U
Hi-Z TO V
V
V
1.69k
– +
OL
OH
U
DAC
TO V
TO Hi-Z
OH
OH
C
LOAD
W
2410 TA03
= 20pF
U
W
ADC
Figure 1. LTC2410 State Transition Diagram
SDO
AUTOCALIBRATION
FALSE
DECIMATING FIR
AND CONTROL
Hi-Z TO V
V
V
OH
OL
V
TO Hi-Z
TO V
DATA OUTPUT
CC
CONVERT
CS = LOW
1.69k
SCK
SLEEP
C
OL
OL
AND
LOAD
TRUE
2410 TA04
= 20pF
2410 F01
OSCILLATOR
INTERFACE
INTERNAL
LTC2410
SERIAL
(INT/EXT)
F
SDO
SCK
CS
7
2410 FD
O

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