LTC2410 Linear Technology, LTC2410 Datasheet - Page 19

• Manufacturer Part Number: LTC2410
• Description: 24-Bit No Latency ADC with Differential Input and Differential Reference
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
Figure 14. CS Capacitance vs Supply Current
Figure 13. CS Capacitance vs Output Rate
300
250
200
150
100
Figure 12. CS Capacitance vs t
50
4
2
0
0
8
7
6
5
3
1
7
6
5
4
3
1
0
2
0
1
1
U
10
10
10
CAPACITANCE ON CS (pF)
CAPACITANCE ON CS (pF)
V
V
CAPACITANCE ON CS (pF)
CC
CC
V
= 5V
= 3V
CC
100
U
100
100
= 5V
1000
1000
1000
V
CC
V
W
CC
= 5V
10000
10000
10000
= 3V
SAMPLE
V
CC
2400 F13
2400 F14
2400 F12
= 3V
100000
100000
100000
U
CS is discharging; therefore, the internal serial clock
timing mode is automatically selected if SCK is floating. It
is important to ensure there are no external drivers pulling
SCK LOW while CS is discharging.
PRESERVING THE CONVERTER ACCURACY
The LTC2410 is designed to reduce as much as possible
the conversion result sensitivity to device decoupling,
PCB layout, antialiasing circuits, line frequency perturba-
tions and so on. Nevertheless, in order to preserve the
extreme accuracy capability of this part, some simple
precautions are desirable.
Digital Signal Levels
The LTC2410’s digital interface is easy to use. Its digital
inputs (F
accept standard TTL/CMOS logic levels and the internal
hysteresis receivers can tolerate edge rates as slow as
100 s. However, some considerations are required to take
advantage of the exceptional accuracy and low supply
current of this converter.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
While a digital input signal is in the range 0.5V to
(V
current from the power supply. It should be noted that,
when any one of the digital input signals (F
in External SCK mode of operation) is within this range, the
LTC2410 power supply current may increase even if the
signal in question is at a valid logic level. For micropower
operation, it is recommended to drive all digital input
signals to full CMOS levels [V
(V
During the conversion period, the undershoot and/or
overshoot of a fast digital signal connected to the LTC2410
pins may severely disturb the analog to digital conversion
process. Undershoot and overshoot can occur because of
the impedance mismatch at the converter pin when the
transition time of an external control signal is less than
twice the propagation delay from the driver to LTC2410.
For reference, on a regular FR-4 board, signal propagation
CC
CC
– 0.5V), the CMOS input receiver draws additional
– 0.4V)].
O
, CS and SCK in External SCK mode of operation)
IL
< 0.4V and V
LTC2410
O
, CS and SCK
19
OH
>