LTC2410 Linear Technology, LTC2410 Datasheet - Page 16

• Manufacturer Part Number: LTC2410
• Description: 24-Bit No Latency ADC with Differential Input and Differential Reference
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
LTC2410
frequency f
HIGH before time t
state. The conversion result is held in the internal static
shift register.
If CS remains LOW longer than t
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 32nd
rising edge. Data is shifted out the SDO pin on each falling
edge of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of the
conversion result on the 32nd rising edge of SCK. After the
32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 32nd rising edge
of SCK, see Figure 9. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
16
(INTERNAL)
SDO
SCK
CS
EOSC
Hi-Z
SLEEP
> t
, then t
EOCtest
EOCtest
BIT 0
EOC
U
EOCtest
CONVERSION
Hi-Z
, the device remains in the sleep
U
DATA OUTPUT
TEST EOC
is 3.6/f
Figure 9. Internal Serial Clock, Reduced Data Output Length
Hi-Z
EOCtest
W
TEST EOC
EOSC
SLEEP
ANALOG INPUT RANGE
, the first rising
Hi-Z
. If CS is pulled
–0.5V
<t
EOCtest
REF
1, 7, 8, 9, 10, 15, 16
BIT 31
0.1V TO V
REFERENCE
U
EOC
TO 0.5V
VOLTAGE
1 F
2.7V TO 5.5V
REF
CC
BIT 30
2
3
4
5
6
V
REF
REF
IN
IN
GND
CC
+
–
LTC2410
new conversion. This is useful for systems not requiring
all 32 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
be avoided by adding an external 10k pull-up resistor to
the SCK pin or by never pulling CS HIGH when SCK is LOW.
Whenever SCK is LOW, the LTC2410’s internal pull-up at
pin SCK is disabled. Normally, SCK is not externally driven
if the device is in the internal SCK timing mode. However,
certain applications may require an external driver on SCK.
If this driver goes Hi-Z after outputting a LOW signal, the
LTC2410’s internal pull-up remains disabled. Hence, SCK
remains LOW. On the next falling edge of CS, the device is
switched to the external SCK timing mode. By adding an
external 10k pull-up resistor to SCK, this pin goes HIGH
once the external driver goes Hi-Z. On the next CS falling
edge, the device will remain in the internal SCK timing
mode.
+
–
BIT 29
SIG
SDO
SCK
CS
F
O
14
13
12
11
DATA OUTPUT
BIT 28
MSB
3-WIRE
SPI INTERFACE
V
BIT 27
CC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
BIT 26
BIT 8
V
CC
10k
CONVERSION
Hi-Z
TEST EOC
2410 F09