cy28rs680 SpectraLinear Inc, cy28rs680 Datasheet - Page 10

• Manufacturer Part Number: cy28rs680
• Description: Clock Generator For Ati Rs5xx/6xx Chipsets
• Manufacturer: SpectraLinear Inc

Rev 1.0, March 28, 2007
Byte 14: ATIG DAF Register1
Byte 15: WDT Recovery Register
Byte 16: Overclocking Support Register
Table 4. Crystal Recommendations
14.31818 MHz
Frequency
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
(Fund)
@Pup
@Pup
@Pup
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Cut
AT
Loading Load Cap
Parallel
RECOVERY_N[7]
RECOVERY_N[6]
RECOVERY_N[5]
RECOVERY_N[4]
RECOVERY_N[3]
RECOVERY_N[2]
RECOVERY_N[1]
RECOVERY_N[0]
ATIG_DAF_N[7]
ATIG_DAF_N[6]
ATIG_DAF_N[5]
ATIG_DAF_N[4]
ATIG_DAF_N[3]
ATIG_DAF_N[2]
ATIG_DAF_N[1]
ATIG_DAF_N[0]
Prog_ATIG_EN
Prog_SRC_EN
Prog_CPU_EN
Recovery_N8
Reserved
Reserved
Reserved
ATIG_N8
Name
Name
Name
20 pF
0.1 mW
(max.)
If Prog_ATIG_EN is set, the values programmed in ATIG_DAF_N[8:0] will
be used to determine the ATIG output frequency.
Used when RESET_IN# is asserted or the Watchdog timer times out. This
will be the safe value or last known good frequency of the CPU. It is set
by the user before engaging in any overclocking exercise. M values revert
to those set by the FS[C:A] pins
ATIG DAF bit N8
Reserved
Reserved
Enables the setting of SRC_PLL (PLL3) N values via byte 8
0 = Disable, 1 = Enable
Enables the setting of ATIG_PLL (PLL2) N values via byte 17
0 = Disable, 1 = Enable
Enables the setting of CPU_PLL (PLL1) M and N values via byte 15 and 16
0 = Disable, 1 = Enable
Reserved
CPU Safe recovery bit 8 for RESET_IN and Watchdog timer timeout.
Drive
Shunt Cap
(max.)
5 pF
Motional
0.016 pF
(max.)
Description
Description
Description
Tolerance
35 ppm
(max.)
CY28RS680
Stability
30 ppm
(max.)
Page 10 of 20
Aging
(max.)
5 ppm