cy28rs680 SpectraLinear Inc, cy28rs680 Datasheet - Page 5

• Manufacturer Part Number: cy28rs680
• Description: Clock Generator For Ati Rs5xx/6xx Chipsets
• Manufacturer: SpectraLinear Inc

Rev 1.0, March 28, 2007
Table 3. Byte Read and Byte Write Protocol
Control Registers
Byte 0: Output Enable Register 0
Byte 1: Output Enable Register 1
27:20
18:11
Bit
Bit
Bit
8:2
10
19
28
29
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
9
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
@Pup
@Pup
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Byte Write Protocol
Description
SRC [T/C]0
ATIG[T/C]3
ATIG[T/C]2
ATIG[T/C]1
ATIG[T/C]0
SRC[T/C]7
SRC[T/C]6
SRC[T/C]5
SRC[T/C]4
SRC[T/C]3
SRC[T/C]2
SRC[T/C]1
Reserved
Reserved
Name
Name
SRC[T/C]7 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]6 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]5 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]4 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Reserved
Reserved
ATIG[T/C]3 Output Enable
0 = Disable (Hi-Z), 1 = Enable
ATIG[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
ATIG[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
ATIG[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
27:21
37:30
18:11
Bit
8:2
10
19
20
28
29
38
39
1
9
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeated start
Slave address – 7 bits
Read
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
Description
Description
Byte Read Protocol
Description
CY28RS680
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