cy28rs680 SpectraLinear Inc, cy28rs680 Datasheet - Page 14

• Manufacturer Part Number: cy28rs680
• Description: Clock Generator For Ati Rs5xx/6xx Chipsets
• Manufacturer: SpectraLinear Inc

Rev 1.0, March 28, 2007
Table 7.) Frequency Table for the CPU Clock (CPU PLLPLL)
Table 6.) Default Divider for all differential clocks
Table 5. Overclocking Table of the RS680
Overclocking
Overclocking
Overclocking
Overclocking
F S C
0
0
0
0
1
1
1
ATIG
CPU
HTT
SRC
C l o c k
A T I G
C P U
S R C
F S B
Function
0
0
1
1
0
0
1
Dial-A-
Dial-A-
Dial-A-
FSEL
Freq
Freq
Freq
Byte10<0> - Smooth Switch Select
Byte13<7>,Byte12<7:0> - CPU_DAF_N[8:0]
Byte13<6:0> - CPU_DAF_M[6:0]
Byte16<2> - Prog_CPU_EN
Select
Byte16<7>,Byte14<7:0> ATIG_DAF_N[8:0]
Byte16<3> - Prog_ATIG_EN
To support 100% Overclocking the
appropriate band has to be chosen using:
ATIG_OC_SEL1 -Byte3<4>
ATIG_OC_SEL0 -Byte3<3>
Byte8<7:0> - SRC_DAF_N[7:0]
Byte16<4> - Prog_SRC_EN
F S A
FSEL_[C:A] -Byte3<2:0> - SW Frequency
0
1
0
1
0
1
0
M D i v i d e r
6 0
6 0
8
C P U A c t u a l
SMB Reg Bits
2 6 6 . 6 7
1 3 3 . 3 3
1 6 6 . 6 7
3 3 3 . 3 3
( M H z )
2 0 0
1 0 0
4 0 0
N A c t u a l
N D i v i d e r
2 0 0
2 0 0
2 0 0
1 7 5
1 7 5
2 0 0
2 0 0
2 0 0
4 4 7
FSB, FSA
None
FSC,
None
None
Pins
N M a x
2 5 5
2 7 9
2 8 0
2 5 2
2 4 7
2 6 0
Refer to the Table-3 for the
M and N values that could
be loaded into the DAF
registers.
Refer to the Table-3 CPU
OC
Overclocked by the same %
as the CPU
Refer to the Table-4 ATIG
OC SEL1 & SEL0 I2C bits
have been implemented as
the FSE pin and
PCI_OC_SEL on the
b30m08a (Lakeport)
Refer to the Table-5 SRC
OC
O D i v i d e r
M | G e a r R a t io
Comments
6 3 | 1 2 0
6 0 | 1 2 0
6 0 | 8 0
6 0 | 4 0
6 0 | 6 0
6 3 | 6 0
4
8
8
CY28RS680
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