cy28rs680 SpectraLinear Inc, cy28rs680 Datasheet - Page 6

• Manufacturer Part Number: cy28rs680
• Description: Clock Generator For Ati Rs5xx/6xx Chipsets
• Manufacturer: SpectraLinear Inc

Rev 1.0, March 28, 2007
Byte 1: Output Enable Register 1 (continued)
Byte 2: Output Enable Register 2
Byte 3: SW_FREQ Selection Register
Byte 4: Spread Spectrum Control Register
Bit
Bit
Bit
Bit
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
@Pup
@Pup
@Pup
@Pup
1
1
0
0
0
1
0
0
1
0
1
1
1
1
1
1
1
0
0
0
0
CPU Spread Enable
ATIG_OC_SEL1
ATIG_OC_SEL0
CPU[T/C]1
CPU[T/C]0
USB_48_1
USB_48_0
ATIG_SS0
CPU_SS1
CPU_SS0
Reserved
Reserved
Reserved
Reserved
FSEL_C
FSEL_B
FSEL_A
REF_2
REF_1
REF_0
HTT66
Name
Name
Name
Name
Reserved
CPU[T/C]1 Output Enable
Reserved
Reserved
Reserved
0 = Disable (Hi-Z), 1 = Enable
CPU[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
USB_48_1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
USB_48_0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
REF_2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
REF_1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
REF_0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
HTT66 Output Enable
0 = Disable (Hi-Z), 1 = Enable
CPU_PLL (PLL1) Spread Spectrum Enable
0= Spread Off, 1 = Spread On
SW Frequency Selection Bits
CPU(PLL1) Spread Spectrum Selection
00: –0.5% (peak to peak)
01: ±0.25% (peak to peak)
10: –1.0% (peak to peak)
11: ±0.5% (peak to peak)
ATIG(PLL2) Spread Spectrum Selection
00: –0.5% (peak to peak)
01: –1.0% (peak to peak)
SEL1
X
0
1
SEL0
0
0
1
111.33–166 MHz
100–125 MHz
166–256 MHz
ATIG Output
Description
Description
Description
Description
CY28RS680
166–250
200–250
166–256
N
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