cy28rs680 SpectraLinear Inc, cy28rs680 Datasheet - Page 9

• Manufacturer Part Number: cy28rs680
• Description: Clock Generator For Ati Rs5xx/6xx Chipsets
• Manufacturer: SpectraLinear Inc

Rev 1.0, March 28, 2007
Byte 11: WDT System Register
Byte 12: CPU DAF Register1
Byte 13: CPU DAF Register2
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
@Pup
@Pup
@Pup
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Recovery_Frequency
CPU_DAF_M[6]
CPU_DAF_M[5]
CPU_DAF_M[4]
CPU_DAF_M[3]
CPU_DAF_M[2]
CPU_DAF_M[1]
CPU_DAF_M[0]
CPU_DAF_N[7]
CPU_DAF_N[6]
CPU_DAF_N[5]
CPU_DAF_N[4]
CPU_DAF_N[3]
CPU_DAF_N[2]
CPU_DAF_N[1]
CPU_DAF_N[0]
CPU_DAF_N[8]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Name
Name
Name
This bit allows selection of the frequency setting that the clock will be
restored to once the system is rebooted
0 = Use HW settings, 1 = Recovery N[8:0]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and
CPU_DAF_M[6:0] will be used to determine the CPU output frequency.
The setting of the FS_Override bit determines the frequency ratio for CPU
and other output clocks. When it is cleared, the same frequency ratio
stated in the Latched FS[D:A] register will be used. When it is set, the
frequency ratio stated in the FSEL[3:0] register will be used.
If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and
CPU_DAF_M[6:0] will be used to determine the CPU output frequency.
The setting of the FS_Override bit determines the frequency ratio for CPU
and other output clocks. When it is cleared, the same frequency ratio
stated in the Latched FS[D:A] register will be used. When it is set, the
frequency ratio stated in the FSEL[3:0] register will be used.
Description
Description
Description
CY28RS680
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