74LV74PW,118 NXP Semiconductors, 74LV74PW,118 Datasheet - Page 16

• Manufacturer Part Number: 74LV74PW,118
• Description: IC DUAL D FF POSEDG TRIG 14TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVr
• Type: D-Typer

Specifications of 74LV74PW,118

• Output Type: Differential
• Package / Case: 14-TSSOP
• Function: Set(Preset) and Reset
• Number Of Elements: 2
• Number Of Bits Per Element: 1
• Frequency - Clock: 56MHz
• Trigger Type: Positive Edge
• Current - Output High, Low: 12mA, 12mA
• Voltage - Supply: 1 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 2
• Logic Family: LV
• Logic Type: D-Type Edge Triggered Flip-Flop
• Polarity: Inverting/Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 11 ns at 3.3 V
• High Level Output Current: - 12 mA
• Low Level Output Current: 12 mA
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 1 V
• Delay Time - Propagation: -
• Technology: CMOS
• Number Of Bits: 2
• Number Of Elements: 2
• Clock-edge Trigger Type: Positive-Edge
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSSOP
• Frequency (max): 56MHz
• Operating Supply Voltage (min): 1V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 14
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Delay Time - Propagation: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 74LV74PW-T; 74LV74PW-T; 935175140118

NXP Semiconductors
Fig 13. Package outline SOT762-1 (DHVQFN14)
74LV74_3
Product data sheet
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
UNIT
mm
VERSION
OUTLINE
SOT762-1
max.
A
1
(1)
terminal 1
index area
0.05
0.00
A 1
terminal 1
index area
E h
L
0.30
0.18
14
1
b
IEC
- - -
0.2
2
c
13
e
D
3.1
2.9
0
(1)
1.65
1.35
D h
e 1
D h
D
MO-241
JEDEC
E
2.6
2.4
(1)
b
Rev. 03 — 28 September 2007
REFERENCES
1.15
0.85
Dual D-type flip-flop with set and reset; positive edge-trigger
E h
9
6
0.5
e
7
8
JEITA
B
- - -
e
scale
w
v
2.5
e 1
2
M
M
A
E
C
C
A
0.5
0.3
L
B
0.1
v
0.05
w
y 1 C
A
A 1
0.05
y
PROJECTION
EUROPEAN
5 mm
0.1
y 1
detail X
X
C
© NXP B.V. 2007. All rights reserved.
y
ISSUE DATE
74LV74
02-10-17
03-01-27
c
SOT762-1
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