sc3200 Advanced Micro Devices, sc3200 Datasheet - Page 46

• Manufacturer Part Number: sc3200
• Description: Geode-tm Sc3200 Processor
• Manufacturer: Advanced Micro Devices

46
Ball
No.
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
5, 2
5, 2
5, 2
5, 2
Signal Name
GPIO1
IOCS1#
TFTD12
TRDE#
GPIO0
V
V
V
V
NC
PE
TFTD14
F_C/BE2#
V
V
PD2
TFTD8
F_AD2
ERR#
TFTD4
F_C/BE0#
AFD#/DSTRB#
TFTD2
INTR_O
V
NC
V
CORE
SS
IO
IO
IO
SS
IO
SS
Table 3-4.
Revision 5.1
(PU/PD)
(PU
(PU
(PU
(PU
(PU
PD
PWR
PWR
PWR
PWR
PWR
GND
GND
GND
I/O
I/O
I/O
I/O
---
---
O
O
O
O
O
O
O
O
O
O
O
O
22.5
I
I
22.5
22.5
22.5
22.5
22.5
)
)
)
)
)
481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued)
Buffer
IN
IN
O
O
O
O
Type
IN
O
O
O
O
O
O
O
O
O
O
IN
T
IN
T
14/14
14/14
14/14
14/14
---
---
---
---
---
---
---
---
---
---
, O
, O
5
4
3/5
1/4
3/5
TS
3/5
1/4
1/4
1/4
1/4
1/4
1/4
T
T
,
,
3/
1/
1
Power
Rail
V
V
V
V
V
V
V
V
V
---
---
---
---
---
---
---
---
---
---
IO
IO
IO
IO
IO
IO
IO
IO
IO
Configuration
PMR[23]
PMR[13] = 0
PMR[23]
PMR[13] = 1
PMR[23]
PMR[12] = 0
PMR[12] = 1
---
---
---
---
---
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
(PU/PD under soft-
ware control.)
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 1 or
FPCI_MON = 1)
---
---
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 1 or
FPCI_MON = 1)
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 1 or
FPCI_MON = 1)
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 1 or
FPCI_MON = 1)
---
---
---
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
= 0 and
= 0 and
= 1
= 0 and
= 1 and
= 0 and
= 0 and
= 1 and
= 0 and
= 0 and
= 1 and
= 0 and
= 0 and
= 1 and
= 0 and
Ball
No.
D26
D27
D28
D29
D30
D31
E1
E2
E3
E4
E28
E29
E30
E31
F1
F2
F3
F4
F28
Signal Name
INTA#
AV
GPIO6
DTR2#/BOUT2
IDE_IOR1#
SDTEST5
SOUT2
CLKSEL2
TDP
TDN
AD16
A16
AD19
A19
AD18
A18
DEVSEL#
BHE#
SIN2
SDTEST3
TRST#
TDO
TCK
TRDY#
D13
IRDY#
D14
C/BE2#
D10
AD17
A17
TMS
CCUSB
AMD Geode™ SC3200 Processor Data Book
(PU/PD)
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PD
PWR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
22.5
22.5
22.5
22.5
22.5
22.5
22.5
22.5
22.5
22.5
22.5
22.5
22.5
22.5
22.5
100
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
Buffer
IN
Diode
WIRE
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Type
IN
IN
IN
IN
IN
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
IN
O
STRP
---
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
TS
1/4
1/4
1/4
2/5
8/8
2/5
PCI
PCI
PCI
TS
,
,
,
,
,
,
,
,
,
,
,
,
1
Power
Rail
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
---
---
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Signal Definitions
Configuration
---
---
PMR[18] = 0 and
PMR[8] = 0
PMR[18] = 1 and
PMR[8] = 0
PMR[18] = 0 and
PMR[8] = 1
PMR[18] = 1 and
PMR[8] = 1
---
Strap (See Table 3-
6 on page 58.)
---
---
Cycle Multiplexed
Cycle Multiplexed
Cycle Multiplexed
Cycle Multiplexed
PMR[28] = 0
PMR[28] = 1
---
---
---
Cycle Multiplexed
Cycle Multiplexed
Cycle Multiplexed
Cycle Multiplexed
---