sc3200 Advanced Micro Devices, sc3200 Datasheet - Page 72

• Manufacturer Part Number: sc3200
• Description: Geode-tm Sc3200 Processor
• Manufacturer: Advanced Micro Devices

3.4.6
72
Signal Name
SERR#
REQ1#
REQ0#
GNT1#
GNT0#
PCI Bus Interface Signals (Continued)
Revision 5.1
EBGA
C1
D2
D4
A9
E3
BalL No.
TEPBGA
H1
C6
C5
A5
B5
Type
I/O
O
I
Description
System Error. SERR# can be asserted by
any agent for reporting errors other than PCI
parity. When the PFS bit is enabled in the
GX1 module’s PCI Control Function 2 regis-
ter (Index 41h[5]), SERR# is asserted upon
assertion of PERR#.
This signal is internally connected to a pull-
up resistor.
Request Lines. REQ[1:0]# indicate to the
arbiter that an agent requires the bus. Each
master has its own REQ# line. REQ# priori-
ties (in order) are:
1)
2)
3)
4)
5)
6)
7)
Each REQ# is internally connected to a pull-
up resistor.
Grant Lines. GNT[1:0]# indicate to the
requesting master that it has been granted
access to the bus. Each master has its own
GNT# line. GNT# can be retracted at any
time a higher REQ# is received or if the mas-
ter does not begin a cycle within a minimum
period of time (16 PCI clocks).
Each of these signals is internally connected
to a pull-up resistor.
GNT0# must have a pull-up resistor of 1.5
KΩ and GNT1# must have a pull-up resistor
of 1.5 KΩ.
VIP
IDE Channel 0
IDE Channel 1
Audio
USB
External REQ0#
External REQ1#.
AMD Geode™ SC3200 Processor Data Book
DID1 (Strap)
DID0 (Strap)
Signal Definitions
Mux
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