sa8027 NXP Semiconductors, sa8027 Datasheet - Page 11

• Manufacturer Part Number: sa8027
• Description: 2.5 Ghz Low Voltage, Low Power Rf Fractional-n/if Integer Frequency Synthesizer
• Manufacturer: NXP Semiconductors

the need for added active switches and reduces external component
Philips Semiconductors
1.7 Charge Pumps
The PHP and PHI charge pumps are driven by the main phase
detector, while the PHA charge pump is driven by the auxiliary
phase detector. The I
the external resistor attached to the R
The charge pump, by default, will automatically go into speed-up
mode (which can deliver up to 15*I
PHI), based on the strobe pulse width following the A word, to
reduce switching speed for large tuning voltage steps (i.e., large
frequency steps). Figure 10 shows the recommended passive loop
filter configuration. Note: This charge pump architecture eliminates
count. Furthermore, the programmable charge pump gains provide
some programmability to the loop filter bandwidth.
The duration of speed-up mode is determined by the strobe pulse
width following the A word. Recommended optimal strobe width is
equal to the total loop filter capacitance charge time from state 1 to
state 2. The strobe width must not exceed this charge time. The
strobe width is controlled by the CPU ( number of clock cycles).
In addition, charge pumps will stay in speed-up mode continuously
while Tspu = 1 (in D word). The speed-up mode can also be
disabled by programming T
2001 Aug 21
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
PHP[PHP–SU]
Figure 10. Typical passive 3-pole loop filter
PHI
SET
value (refer to Table 1) is determined by
R1
dis-spu
C1
= 1 (in D word).
SET
C2
SET
R2
for PHP_SU, and 36*I
pin.
C3
SR02356
VCO
SET
for
11
1. I
2. CP1 is used to disable the PHI pump, I
condition. The lock condition for the main and auxiliary synthesizers
Table 1. Main and auxiliary charge pump currents
NOTES:
1.8 Lock Detect
The output LOCK maintains a logic ‘1’ when the auxiliary phase
detector (AND/ORed) with the main phase detector indicates a lock
is defined as a phase difference of less than
frequency at the input REF
condition when the other counter is powered down. Out of lock
(logic ‘0’) is indicated when both counters are powered down.
1.9 Power-down mode
The power-down signal can be either hardware (PON) or software
(PD). The PON signal is exclusively ORed with the PD bits in
B-word. If PON = 0, then the part is powered up when PD = 1. PON
can be used to invert the polarity of the software bit PD. When the
synthesizer is reactivated after power-down, the main and reference
dividers are synchronized to avoid possibility of random phase
errors on power-up.
CP1
at pin PHP during speed up condition.
0
0
1
1
SET
= V
CP0
SET
0
1
0
1
/R
SET
1.5xl
0.5xl
1.5xl
0.5xl
I
: bias current for charge pumps.
PHA
SET
SET
SET
SET
in+, –
3xI
1xl
3xl
1xl
. One counter can fulfill the lock
I
PHP
SET
SET
SET
SET
PHP–SU
I
15xl
15xl
PHP–SU
5xl
5xl
1 period of the
SET
SET
SET
SET
is the total current
SA8027
Product data
36xl
12xl
I
PHI
0
0
SET
SET