sa8027 NXP Semiconductors, sa8027 Datasheet - Page 14

• Manufacturer Part Number: sa8027
• Description: 2.5 Ghz Low Voltage, Low Power Rf Fractional-n/if Integer Frequency Synthesizer
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Data format
Table 2. Format of programmed data
Table 3. A word, length 24 bits
Table 4. B word, length 24 bits
Table 5. C word, length 24 bits
Table 6. D word, length 24 bits
2001 Aug 21
Last In
Address
A word address
Fractional Modulus select
Fractional-N Increment
N-Divider
Spare
B word address
REF-Divider
Lock detect output
Power down (PD)
Fractional Compensation
C word address
A-Divider
Charge pump current Ratio
Main comparison select
Aux comparison select
D word address
T
T
Default
Address
1
dis-spu
spu
0
Address
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
0
1
Default
Default
Address
Last In
Default
= 1
p23
1
0
= 1
0
1
fmod
fmod
0
0
A13
R9
0
0
–
0
Fractional-N
NF2
R8
A12
0
0
0
p22
–
0
NF1
R7
0
1
A11
0
Fixed to 01
R0..R9, Reference divider values 4 to 1023 allowed for divider ratio. R <9:0>.
L1 L0
0 0 Combined main, aux. lock detect signal present at the LOCK pin (push/pull).
0 1 Combined main, aux, lock detect signal present at the LOCK pin (open drain).
1 0 Main lock detect signal present at the LOCK pin (push/pull).
1 1 Auxiliary loop lock detect signal present at the LOCK pin (push/pull).
When auxiliary loop and main loop are in power down mode, the lock indicator is low.
PON pin is tied to GND
PON pin is tied to V
FC7..0 Fractional Compensation charge pump current DAC, values 0 to 255.
–
0
Reference Divider
R6
Fixed to 00.
fmod = 0 is modulo 8; fmod = 1 is modulo 5.
Fractional-N Increment values 000 to 111 (0 to 7). NF is a 3-bit word.
N0..N15, Main divider values 512 to 65535 allowed for divider ratio.
SK1, SK2 must be set to 0.
NF0
1
Fixed to 10
A0..A13, Auxiliary divider values 128 to 16383 allowed for divider ratio.
CP1, CP0: Charge pump current ratio, see Table 1.
SM comparison divider select for main phase detector.
SA Comparison divider select for auxiliary phase detector.
0
A10
0
Fixed to 110.
Speed-up mode disabled. NOTE: All other test bits must be set to 0 for normal operation.
Speed-up mode always on. NOTE: All other test bits must be set to 0 for normal operation.
–
0
R5
0
MSB
Main Divider ratio
A9
N15
0
0
T
MSB
p21
dis-spu
R4
1
Auxiliary Divider
0
A8
1
N14
0
R3
0
A7
Tspu
DD
1
0
N13
1
R2
0
A6
1
N12
–
0
Main = 1: power-on to Main PLL. Main = 0: power-down to Main PLL.
Aux = 1: power-on to Aux PLL. Aux = 0: power-down to Aux PLL.
Main = 0: power-on to Main PLL. Main = 1: power-down to Main PLL.
Aux = 0: power-on to Aux PLL. Aux = 1: power-down to Aux PLL.
0
R1
0
p20
A5
0
N11
–
0
R0
0
1
A4
0
Synthesizer Test Bits
N10
L1
–
0
0
0
14
Lock
A3
1
Serial Programming Format
N9
L0
0
–
0
1
A2
0
../..
Main
N8
–
0
0
1
A1
1
PD
N7
0
–
0
Aux
A0
0
1
N6
0
–
0
CP1
FC7
1
0
CP
../..
N5
FDAC (Fractional Compensation DAC)
1
–
0
CP0
FC6
1
1
N4
1
–
0
SM2
FC5
0
0
N3
0
–
0
SM
SM1
FC4
0
1
N2
0
p1
–
0
SM0
FC3
0
N1
0
0
–
0
SA2
LSB
FC2
0
N0
0
0
SA8027
First In LSB
–
0
SA1
FC1
Product data
SK1
SA
0
0
0
First In
p0
Spare
–
0
SA0
SK2
FC0
0
0
0
–
0