74AHCT377PW,112 NXP Semiconductors, 74AHCT377PW,112 Datasheet

IC OCTAL D F-F POS-EDGE 20-TSSOP

74AHCT377PW,112

Manufacturer Part Number
74AHCT377PW,112
Description
IC OCTAL D F-F POS-EDGE 20-TSSOP
Manufacturer
NXP Semiconductors
Series
74AHCTr
Type
D-Type Busr
Datasheet

Specifications of 74AHCT377PW,112

Package / Case
20-TSSOP
Function
Standard
Output Type
Non-Inverted
Number Of Elements
1
Number Of Bits Per Element
8
Frequency - Clock
130MHz
Delay Time - Propagation
5.7ns
Trigger Type
Positive Edge
Current - Output High, Low
8mA, 8mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Number Of Circuits
1
Logic Family
AHCT
Logic Type
D-Type Edge Triggered Flip-Flop
Polarity
Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
4 ns
High Level Output Current
- 8 mA
Supply Voltage (max)
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Supply Voltage (min)
4.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-2521-5
935267993112
1. General description
2. Features
The 74AHC377; 74AHCT377 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC377; 74AHCT377 has eight edge-triggered, D-type flip-flops with individual D
inputs and Q outputs. A common clock input (CP) loads all flip-flops simultaneously when
the data enable input (E) is LOW. The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the
flip-flop. The E input is only required to be stable one set-up time prior to the
LOW-to-HIGH transition for predictable operation.
For versions associated with the 74AHC377; 74AHCT377, refer to the following:
I
I
I
I
I
I
I
I
I
I
74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
Rev. 02 — 12 June 2008
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than V
Ideal for addressable register applications
Data enable for address and data synchronization
Eight positive-edge triggered D-type flip-flops
Input levels:
ESD protection:
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
For the master reset version, see 74AHC273; 74AHCT273
For the transparent latch version, see 74AHC373; 74AHCT373
For the 3-state version, see 74AHC374; 74AHCT374
N
N
N
N
N
For 74AHC377: CMOS level
For 74AHCT377: TTL level
HBM EIA/JESD22-A114E exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101C exceeds 1000 V
CC
Product data sheet

Related parts for 74AHCT377PW,112

74AHCT377PW,112 Summary of contents

Page 1

Octal D-type flip-flop with data enable; positive-edge trigger Rev. 02 — 12 June 2008 1. General description The 74AHC377; 74AHCT377 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL specified ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74AHC377 74AHC377D +125 C 74AHC377PW +125 C 74AHCT377 74AHCT377D +125 C 74AHCT377PW +125 C 4. Functional diagram Fig 1. Functional diagram 74AHC_AHCT377_2 Product data sheet 74AHC377; 74AHCT377 Octal D-type flip-flop with data enable; positive-edge trigger ...

Page 3

... NXP Semiconductors Fig 2. Logic symbol FF1 CP Q0 Fig 4. Logic diagram 74AHC_AHCT377_2 Product data sheet 74AHC377; 74AHCT377 Octal D-type flip-flop with data enable; positive-edge trigger mna918 Fig FF2 FF3 FF4 Rev. 02 — 12 June 2008 11 1C2 mna919 IEC logic symbol FF5 FF6 ...

Page 4

... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 5. Pin configuration SO20 and TSSOP20 5.2 Pin description Table 2. Pin description Symbol Pin GND 74AHC_AHCT377_2 Product data sheet 74AHC377; 74AHCT377 Octal D-type flip-flop with data enable; positive-edge trigger 377 GND mna917 Description data enable input (active LOW) fl ...

Page 5

... NXP Semiconductors 6. Functional description [1] Table 3. Function table Operating mode Load 1 Load 0 Hold (do nothing) [ HIGH voltage level HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition LOW voltage level LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; = LOW-to-HIGH CP transition; ...

Page 6

... NXP Semiconductors 8. Recommended operating conditions Table 5. Operating conditions Symbol Parameter 74AHC377 V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 74AHCT377 V supply voltage CC V input voltage I V output voltage O T ambient temperature ...

Page 7

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I input leakage GND current 5 supply current 5 input capacitance 74AHCT377 V HIGH-level input voltage V LOW-level input voltage V HIGH-level output voltage 8 LOW-level output voltage ...

Page 8

... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions 74AHC377 t propagation CP to Qn; see pd delay maximum see Figure 6 max frequency pulse width CP HIGH or LOW; W see Figure 3 3.6 V ...

Page 9

... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions 74AHCT377 4 5 propagation CP to Qn; see pd delay maximum see Figure 6 max frequency pulse width CP HIGH or LOW; W see Figure 6 t set-up time Dn CP; see su t hold time Dn ...

Page 10

... NXP Semiconductors 11. Waveforms CP input Qn output Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 6. Clock pulse width, maximum frequency and input to output propagation delays E input Dn input CP input Measurement points are given in The shaded areas indicate when the input is permitted to change for predictable output performance. ...

Page 11

... NXP Semiconductors Test data is given in Table Definitions test circuit termination resistance should be equal to output impedance load capacitance including jig and probe capacitance. L Fig 8. Load circuitry for measuring switching times Table 9. Test data Type Input V I 74AHC377 V CC 74AHCT377 3.0 V 74AHC_AHCT377_2 Product data sheet Octal D-type fl ...

Page 12

... NXP Semiconductors 12. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 13

... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 14

... Document ID Release date 74AHC_AHCT377_2 20080612 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table 74AHC_AHCT377_1 20000815 74AHC_AHCT377_2 Product data sheet 74AHC377 ...

Page 15

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 16

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 Revision history ...

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