32c408b Maxwell Technologies, 32c408b Datasheet - Page 6

• Manufacturer Part Number: 32c408b
• Description: 4 Megabit 512k X 8-bit Sram
• Manufacturer: Maxwell Technologies

1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going low and
3. t
4. t
5. t
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write
8. IC CS goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state.
9. D
10.When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
4 Megabit (512K x 8-Bit) SRAM
F
IGURE
WE going low: A write ends at the earliest transition among CS going high or WE going high. t
of write to end of write.
of the output must not be applied because bus contention can occur.
cycle.
applied.
CW
AS
WR
OUT
is measured from the address valid to the beginning of write.
is measured from the later of CS going low to end of write.
is measured from the end of write to the address change. TWR applied in case a write ends as CS or WE going high.
is the read data of the new address.
3. T
IMING
W
F
AVEFORM OF
IGURE
2. T
IMING
R
EAD
W
C
AVEFORM OF
YCLE (1)
05.02.02 Rev 7
(A
DDRESS
W
RITE
C
C
YCLE
ONTROLLED
All data sheets are subject to change without notice
(OE L
, CS = OE = V
OW
F
WP
IXED
is measured from beginning
)
©2002 Maxwell Technologies
32C408B
IL
, WE = V
All rights reserved.
IH
)
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