S25FL008K Meet Spansion Inc., S25FL008K Datasheet - Page 16

• Manufacturer Part Number: S25FL008K
• Description: 8-mbit Cmos 3.0 Volt Flash Memory With 104-mhz Spi Serial Peripheral Interface Multi I/o Bus
• Manufacturer: Meet Spansion Inc.

6.2
16
Instructions
Notes:
1. X = don’t care
2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored
The instruction set of the S25FL008K consists of thirty five basic instructions that are fully controlled through
the SPI bus (see
Select (CS#). The first byte of data clocked into the SI input provides the instruction code. Data on the SI
input is sampled on the rising edge of clock with most significant bit (MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data
bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the
rising edge of edge CS#. Clock relative timing diagrams for each instruction are included in the figures below.
All read instructions can be completed after any clocked bit. However, all instructions that Write, Program or
Erase must complete on a byte boundary (CS# driven high after a full 8-bits have been clocked) otherwise the
instruction will be ignored. This feature further protects the device from inadvertent writes. Additionally, while
the memory is being programmed or erased, or when the Status Register is being written, all instructions
except for Read Status Register will be ignored until the program or erase cycle has completed.
SEC
X
0
0
0
0
0
0
0
0
X
1
1
1
1
1
1
1
1
TB
X
X
Status Register
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
BP2
Table 6.6
0
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
0
1
D a t a
(1)
BP1
0
0
1
1
0
0
1
1
0
1
0
1
1
0
0
1
1
0
Table 6.3 Status Register Memory Protection (CMP = 1)
to
Table 6.8 on page
BP0
0
1
0
1
0
1
0
1
0
1
1
0
1
X
1
0
1
X
S h e e t
S25FL008K
Block(s)
0 thru 15
0 thru 14
0 thru 13
0 thru 11
1 thru 15
2 thru 15
4 thru 15
8 thru 15
0 thru 15
0 thru 15
0 thru 15
0 thru 15
0 thru 15
0 thru 15
0 thru 15
0 thru 15
0 thru 7
None
( A d v a n c e
19). Instructions are initiated with the falling edge of Chip
S25FL008K (8 MBit) Memory Protection
000000h – 0EFFFFh
000000h – 0DFFFFh
000000h – 0BFFFFh
000000h – 0FEFFFh
000000h – 0FDFFFh
000000h – 0FBFFFh
000000h – 0FFFFFh
000000h – 07FFFFh
010000h – 0FFFFFh
020000h – 0FFFFFh
040000h – 0FFFFFh
080000h – 0FFFFFh
000000h – 0F7FFFh
001000h – 0FFFFFh
002000h – 0FFFFFh
004000h – 0FFFFFh
008000h – 0FFFFFh
Addresses
None
I n f o r m a t i o n )
S25FL008K_00_01 July 30, 2010
1,020 KB
1,016 KB
1,008 KB
1,020 KB
1,016 KB
1,008 KB
Density
960 KB
896 KB
768 KB
512 KB
992 KB
960 KB
896 KB
768 KB
512 KB
992 KB
1 MB
None
(2)
Lower 255/256
Lower 127/128
Upper 255/256
Upper 127/128
Lower 15/16
Upper 15/16
Lower 63/64
Lower 31/32
Upper 63/64
Upper 31/32
Lower 7/8
Lower 3/4
Lower 1/2
Upper 7/8
Upper 3/4
Upper 1/2
Portion
None
All