S25FL008K Meet Spansion Inc., S25FL008K Datasheet - Page 36

• Manufacturer Part Number: S25FL008K
• Description: 8-mbit Cmos 3.0 Volt Flash Memory With 104-mhz Spi Serial Peripheral Interface Multi I/o Bus
• Manufacturer: Meet Spansion Inc.

36
6.2.19
6.2.20
Sector Erase (20h)
32 KB Block Erase (52h)
The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all 1s
(FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase Instruction
(Status Register bit WEL must equal 1). The instruction is initiated by driving the CS# pin low and shifting the
instruction code “20h” followed a 24-bit sector address (A23-A0)
Erase instruction sequence is shown in
The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Sector Erase instruction will not be executed. After CS# is driven high, the self-timed Sector Erase instruction
will commence for a time duration of t
Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status
of the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is
finished and the device is ready to accept other instructions again. After the Sector Erase cycle has finished
the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase instruction will not
be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0)
bits
The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of all 1s
(FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction
(Status Register bit WEL must equal 1). The instruction is initiated by driving the CS# pin low and shifting the
instruction code “52h” followed a 24-bit block address (A23-A0)
Erase instruction sequence is shown in
The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Block Erase instruction will not be executed. After CS# is driven high, the self-timed Block Erase instruction
will commence for a time duration of t
Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status
of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished
and the device is ready to accept other instructions again. After the Block Erase cycle has finished the Write
Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed
if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see
Table 6.2, Status Register Memory Protection (CMP = 0) on page
(Table 6.2, Status Register Memory Protection (CMP = 0) on page
CLK
SIO
CS#
SO
Mode 3
Mode 0
D a t a
Figure 6.24 Sector Erase Instruction Sequence Diagram
= MSB
0
S h e e t
1
SE
BE1
Instruction (20h)
Figure 6.24 on page
2
Figure
S25FL008K
.
See AC Electrical Characteristics on page 54.
(See AC Electrical Characteristics on page
3
( A d v a n c e
4
6.25.
5
High Impedance
6
7
23 22
8
36.
9
24-Bit Address
See Block Diagram on page 8.
I n f o r m a t i o n )
See Block Diagram on page 8.
15).
15).
2
29 30 31
1
S25FL008K_00_01 July 30, 2010
0
Mode 0
Mode 3
54.). While the Block
While the Sector
The Block
The Sector