S25FL128K Meet Spansion Inc., S25FL128K Datasheet - Page 12

• Manufacturer Part Number: S25FL128K
• Description: 128-mbit Cmos 3.0 Volt Flash Memory With 104-mhz Spi Serial Peripheral Interface Multi I/o Bus
• Manufacturer: Meet Spansion Inc.

5.2
6. Control and Status Registers
12
5.2.1
Write Protection
Write Protect Features
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern, the S25FL128K
provides several means to protect the data from inadvertent writes.
 Device resets when V
 Time delay write disable after Power-up
 Write enable/disable instructions and automatic write disable after erase or program
 Software and Hardware (WP# pin) write protection using Status Register
 Write Protection using Deep Power-down instruction
 Lock Down write protection until next power-up
 One Time Program (OTP) write protection
Upon power-up or at power-down, the S25FL128K will maintain a reset condition while V
threshold value of VWI (see
operations are disabled and no instructions are recognized. During power-up and after the V
exceeds VWI, all program and erase related instructions are further disabled for a time delay of t
includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status
Register instructions. Note that the chip select pin (CS#) must track the V
V
this.
After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector
Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a
program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write-disabled
state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting the
Status Register Protect (SRP0, SRP1) and Block Protect (CMP, SEC,TB, BP2, BP1 and BP0) bits. These
settings allow a portion as small as 4 kB sector or the entire memory array to be configured as read only.
Used in conjunction with the Write Protect (WP#) pin, changes to the Status Register can be enabled or
disabled under hardware control.
Deep Power-down instruction offers an extra level of write protection as all instructions are ignored except for
the Release from Deep Power-down instruction.
The Read Status Register-1 and Status Register-2 instructions can be used to provide status on the
availability of the Flash memory array, if the device is write enabled or disabled, the state of write protection,
Quad SPI setting, Security Register lock status and Erase/Program Suspend status. The Write Status
Register instruction can be used to configure the device write protection features, Quad SPI setting and
Security Register OTP lock. Write access to the Status Register is controlled by the state of the non-volatile
Status Register Protect bits (SRP0, SRP1), the Write Enable instruction, and during Standard/Dual SPI
operations, the WP# pin.
CC
-min level and t
VSL
time delay is reached. If needed a pull-up resistor on CS# can be used to accomplish
CC
is below threshold
Figure 7.1, Power-up Timing and Voltage Levels on page
D a t a
See Status Register on page 13.
S25FL128K
S h e e t
( P r e l i m i n a r y )
for further information. Additionally, the
CC
supply level at power-up until the
S25FL128K_00_02 April 1, 2011
53). While reset, all
CC
is below the
CC
voltage
PUW
. This