S25FL128K Meet Spansion Inc., S25FL128K Datasheet - Page 22

• Manufacturer Part Number: S25FL128K
• Description: 128-mbit Cmos 3.0 Volt Flash Memory With 104-mhz Spi Serial Peripheral Interface Multi I/o Bus
• Manufacturer: Meet Spansion Inc.

22
6.2.6
Read Data (03h)
CLK
The Read Data instruction allows one or more data bytes to be sequentially read from the memory. The
instruction is initiated by driving the CS# pin low and then shifting the instruction code “03h” followed by a 24-
bit address (A23-A0) into the SI pin. The code and address bits are latched on the rising edge of the CLK pin.
After the address is received, the data byte of the addressed memory location will be shifted out on the SO
pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically incremented to
the next higher address after each byte of data is shifted out allowing for a continuous stream of data. This
means that the entire memory can be accessed with a single instruction as long as the clock continues. The
instruction is completed by driving CS# high.
The Read Data instruction sequence is shown in
Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects
on the current cycle. The Read Data instruction allows clock rates from DC to a maximum of f
Electrical Characteristics on page
CLK
CS#
CS#
SO
SO
SI
SI
= MSB
= MSB
Mode 3
Mode 0
Mode 3
Mode 0
0
0
1
1
Instruction (01h)
Instruction (03h)
Figure 6.7 Write Status Register Instruction Sequence Diagram
2
2
3
3
Figure 6.8 Read Data Instruction Sequence Diagram
4
4
D a t a
5
High Impedance
5
High Impedance
54.).
6
6
S25FL128K
7
7
S h e e t
7
23 22 21
8
8
6
9
9
Status Register In
Figure
24-Bit Address
5
10
10
4
11 12 13 14 15 16 17
( P r e l i m i n a r y )
3
6.8. If a Read Data instruction is issued while an
3
28 29 30 31 32
2
2
1
1
0
0
X
7
X
6
33 34 35 36 37 38 39
X
18 19
5
S25FL128K_00_02 April 1, 2011
Data Out 1
X
4
X
20 21 22 23
3
X
2
9
1
R
8
(see
0
Mode 3
Mode 0
7
Data Out 2
See AC