S25FL128K Meet Spansion Inc., S25FL128K Datasheet - Page 19

• Manufacturer Part Number: S25FL128K
• Description: 128-mbit Cmos 3.0 Volt Flash Memory With 104-mhz Spi Serial Peripheral Interface Multi I/o Bus
• Manufacturer: Meet Spansion Inc.

April 1, 2011 S25FL128K_00_02
6.2.1
6.2.2
Write Enable (06h)
Write Enable for Volatile Status Register (50h)
Notes:
1. The Device ID will repeat continuously until CS# terminates the instruction.
2. See Manufacturer and Device Identification table for Device ID information.
3. Security Register Address:
The Write Enable instruction
The WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, Block Erase, Chip
Erase, Write Status Register and Erase/Program Security Registers instruction. The Write Enable instruction
is entered by driving CS# low, shifting the instruction code “06h” into the Data Input (SI) pin on the rising edge
of CLK, and then driving CS# high.
The non-volatile Status Register bits described in
to as volatile bits. This gives more flexibility to change the system configuration and memory protection
schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the
Status Register non-volatile bits. To write the volatile values into the Status Register bits, the Write Enable for
Volatile Status Register (50h) instruction must be issued prior to a Write Status Register (01h) instruction.
Release Power down / Device ID
Manufacturer/ Device ID
Manufacturer/Device ID by Dual
I/O
Manufacture/Device ID by Quad
I/O
JEDEC ID
Read Unique ID
Read SFDP Register
Erase Security Registers
Program Security Registers
Read Security Registers
Security Register 1: A23-16 = 00h; A15-8 = 10h; A7-0 = byte address
Security Register 2: A23-16 = 00h; A15-8 = 20h; A7-0 = byte address
Security Register 3: A23-16 = 00h; A15-8 = 30h; A7-0 = byte address
Instruction Name
CLK
CS#
SO
SI
D a t a
Mode 3
Mode 0
(2)
(3)
(3)
S h e e t
(3)
Figure 6.3 Write Enable Instruction Sequence Diagram
Byte 1 (Code)
Table 6.8 Instruction Set (ID, Security Instructions)
(Figure
ABh
5Ah
90h
92h
94h
9Fh
4Bh
44h
42h
48h
( P r e l i m i n a r y )
6.3) sets the Write Enable Latch (WEL) bit in the Status Register to a 1.
0
S25FL128K
A23-A0, M[7:0]
Manufacturer
1
(MF7-MF0)
A23 -A16
A23-A16
A23-A16
dummy
dummy
A23-A8
dummy
Byte 2
00h
Instruction (06h)
High Impedance
2
Section 6.1, Status Register on page 13
3
xxxx, (MF[7:0],
A7-A0, M[7:0]
Memory Type
(ID15-ID8)
A15-A8
A15-A8
A15-A8
dummy
dummy
ID[7:0])
dummy
Byte 3
4
00h
5
6
ID[7:0], …)
(ID7-ID0)
(MF[7:0],
(MF[7:0],
Capacity
dummy
ID[7:0])
dummy
Byte 4
A7-A0
A7-A0
A7-A0
A7-A0
00h
7
Mode 0
Mode 3
(ID7-ID0)
(MF7-MF0)
dummy
dummy
dummy
Byte 5
(D7-0)
can also be written
(1)
(ID63-ID0)
(ID7-ID0)
Byte 6
(D7-0)
(D7-0)
(D7-0)
19