ad5669rbruz Analog Devices, Inc., ad5669rbruz Datasheet - Page 11

• Manufacturer Part Number: ad5669rbruz
• Description: Octal, 12-/16-bit Dac, I C , 5ppm/
• Manufacturer: Analog Devices, Inc.

AD5629R/AD5669R
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
16-Lead
LFCSP
15
16
1
2
11
3
10
6
7
4
9
5
8
12
13
14
Pin No.
16-Lead
TSSOP
1
2
3
4
13
5
12
8
9
6
11
7
10
14
15
16
V
V
OUT
OUT
OUT
DD
A
Figure 2. 16-Lead LFCSP (CP-16-17)
1
2
3
4
A D 5 6 6 9 R/29R
Mnemonic
LDAC
A0
V
V
V
V
V
V
CLR
V
V
V
V
GND
SDA
SCL
DD
OUT
OUT
OUT
OUT
REFIN
OUT
OUT
OUT
OUT
V IE W
TO P
A
B
C
D
E
F
G
H
/V
REFOUT
12
11
10
9
V
V
OUT
OUT
OUT
Description
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have
new data. This allows all DAC outputs to simultaneously update. Alternatively, this pin can be
tied permanently low.
Address Input. Sets the least significant bit of the 7-bit slave address.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should
be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
The AD5629R/AD5669R has a common pin for reference input and reference output. When
using the internal reference, this is the reference output pin. When using an external
reference, this is the reference input pin. The default for this pin is as a reference input.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC
pulses are ignored. When CLR is activated, the input register and the DAC register are
updated with the data contained in the CLR code register—zero, midscale, or full scale.
Default setting clears the output to 0 V.
Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on
the falling edge of the serial clock input.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial
clock input.
D
F
Rev. PrA | Page 11 of 33
V
R E F IN
/V
R E FO U T
V
V
V
V
L D A C
Figure 3. 16-Lead TSSOP (RU-16)
A0
O U T
O U T
O U T
O U T
Preliminary Technical Data
V
D D
C
G
A
E
1
2
3
4
5
6
7
8
(N o t to S cale)
A D 5 6 2 9R/
A D 5 6 6 9R
TO P V IE W
16
1 5
1 4
1 3
1 2
11
1 0
9
S C L
SDA
G N D
V
V
V
V
C L R
O U T
O U T
O U T
O U T
B
D
F
H