ad5669rbruz Analog Devices, Inc., ad5669rbruz Datasheet - Page 28

• Manufacturer Part Number: ad5669rbruz
• Description: Octal, 12-/16-bit Dac, I C , 5ppm/
• Manufacturer: Analog Devices, Inc.

AD5629R/AD5669R
0
1
1
Table 14 for the contents of the input shift register during power-
down/power-up operation. When using the internal reference,
only all channel power-down to the selected modes is
supported.
When both bits are set to 0, the part works normally with its
normal power consumption of 1.3 mA at 5 V. However, for the
three power-down modes, the supply current falls to 0.4 µA at
5 V (0.2 µA at 3 V). Not only does the supply current fall, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode. There are three different
options. The output is connected internally to GND through
either a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited
(three-state). The output stage is illustrated in Figure 77.
The bias generator of the selected DAC(s), output amplifier,
resistor string, and other associated linear circuitry are shut
down when the power-down mode is activated. The internal
reference is powered down only when all channels are powered
down. However, the contents of the DAC register are unaffected
when in power-down. The time to exit power-down is typically
4 µs for V
Any combination of DACs can be powered up by setting PD1
and PD0 to 0 (normal operation). The output powers up to the
DD
1
0
1
= 5 V and for V
2.5V interenal reference on
Internal reference off
1.25V internal reference on
DD
= 3 V. See Figure 47 for a plot.
Rev. PrA | Page 28 of 33
value in the input register ( LDAC low) or to the value in the
DAC register before powering down ( LDAC high).
CLEAR CODE REGISTER
The AD5629R/AD5669R have a hardware CLR pin that
is an asynchronous clear input. The CLR input is falling edge
sensitive. Bringing the CLR line low clears the contents of the
input register and the DAC registers to the data contained in
the user-configurable CLR register and sets the analog outputs
accordingly. This function can be used in system calibration to load
zero scale, midscale, or full scale to all channels together. These
clear code values are user-programmable by setting two bits,
Bit DB1 and Bit DB0, in the CLR control register (see
Table 15). The default setting clears the outputs to 0 V.
Command 0101 is reserved for loading the clear code register
(see Table 8).
The part exits clear code mode on the 32
write to the part. If CLR is activated during a write sequence, the
write is aborted.
The CLR pulse activation time—the falling edge of CLR to
when the output starts to change—is typically 280 ns. However, if
outside the DAC linear region, it typically takes 520 ns after
executing CLR for the output to start changing (see Figure 67).
See Table 16 for contents of the input shift register during the
loading clear code register operation.
Preliminary Technical Data
nd
falling edge of the next