ad5669rbruz Analog Devices, Inc., ad5669rbruz Datasheet - Page 27

• Manufacturer Part Number: ad5669rbruz
• Description: Octal, 12-/16-bit Dac, I C , 5ppm/
• Manufacturer: Analog Devices, Inc.

AD5629R/AD5669R
INPUT SHIFT REGISTER
The input shift register is 24 bits wide. Data is loaded into the
device as a 24-bit word under the control of a serial clock input,
SCL. The timing diagram for this operation is shown in Figure
X. The eight MSBs make up the command byte. DB23-DB20
are the command bits (C3, C2, C1, and C0) that control the
mode of operation of the device. See Table 9 for details. The last
four bits of the first byte are the address bits (A3, A2, A1, and
A0). See Table 10 for details. The rest of the bits are the 16-/12-
bit data word. The data word comprises the 16-/12-bit input
code followed by four don’t cares for the device (see Figure 57
and Figure 58).
MULTIPLE BYTE OPERATION
INTERNAL REFERENCE REGISTER
The internal reference is available on all versions. The on-board
reference is off at power-up by default. This allows the use of an
external reference if the application requires it. The on-board
reference can be turned on or off by a user-programmable
internal REF register by setting Bit DB0 high or low (see Table
10). DB1 selects the internal reference value. When DB1 is set
to 1 the 1.25V reference is selected. When DB1 is set to 0 the
2.5V internal reference is selected. Command 1000 is reserved
for setting the internal REF register (see Table 8). Table 12
shows how the state of the bits in the input shift register
corresponds to the mode of operation of the device. Command
1000 is not functional in AD5669/29 models because there is no
internal reference available.
POWER-ON RESET
The AD5629R/AD5669R family contains a power-on reset
circuit that controls the output voltage during power-up. The
AD5629R/AD5669R DAC output powers up to 0 V, and the
AD5669R-3 DAC output powers up to midscale. The output
remains powered up at this level until a valid write sequence is
D B 23 D B 22 D B 21 D B 20 D B 19 D B 18 D B 17 D B 16 D B 15 D B 14 D B 13 D B 12 D B 11 D B 10
D B 23 D B 22 D B 21 D B 20 D B 19 D B 18 D B 17 D B 16 D B 15 D B 14 D B 13 D B 12 D B 11 D B 10
C3
C3
C O M M A N D
C O M M A N D
C2
C2
C 1
C 1
C O M M A N D B Y T E
C O M M A N D B Y T E
C 0
C 0
A3
A3
D A C A D D R E S S
D A C A D D R E S S
A 2
A 2
A 1
A 1
A 0
A 0
D 15
D 11
Figure 75. AD5669R/AD5669 Input Register Contents
Figure 76. AD5629R/AD5629 Input Register Contents
D 14
D 10
D 13
D 9
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D A T A H IG H B Y T E
D A T A H IG H B Y T E
D 12
D A C D A T A
D 8
D A C D A T A
D 11
D 7
Multiple byte operation is supported on the AD5629R
/AD5669R.Command 1001 is reserved for multiple byte
operation(see Table 8) A 2-byte operation is useful for
applications that require fast DAC updating and do not need to
change the command byte. The S bit (DB22) in the command
register can be set to 1 for 2-byte mode of operation (see Figure
62). For standard 3-byte and 4-byte operation, the S bit (DB22)
in the command byte should be set to 0 (see Figure 61).
made to the DAC. This is useful in applications where it is
important to know the state of the output of the DAC while it is
in the process of powering up. There is also a software
executable reset function that resets the DAC to the power-on
reset code. Command 0111 is reserved for this reset function
(see Table 8). Any events on LDAC or CLR during power-on
reset are ignored.
POWER-DOWN MODES
The AD5629R/AD5669R contain four separate modes
of operation. Command 0100 is reserved for the power-down
function (see Table 8). These modes are software-programmable
by setting two bits, Bit DB9 and Bit DB8, in the control register.
Table 12 shows how the state of the bits corresponds to the
mode of operation of the device. Any or all DACs (DAC H to
DAC A) can be powered down to the selected mode by setting
the corresponding eight bits (DB7 to DB0) to 1. See Table 13.
Internal reference setup
DB9
0
D 10
D 6
D B 9
D B 9
D 9
D 5
DB8
0
D B 8
D B 8
D 8
D 4
D B 7
D B 7
D 7
D 3
Preliminary Technical Data
Operating Mode
Internal reference off
D B 6
D B 6
D 6
D 2
D B 5
D B 5
D 5
D 1
D A T A L O W B Y T E
D A T A L O W B Y T E
D B 4
D B 4
D A C D A T A
D A C D A T A
D 4
D 0
D B 3
D B 3
D 3
X
D B 2
D B 2
D 2
X
D B 1
D B 1
D 1
X
D B 0
D B 0
D 0
X