ad5669rbruz Analog Devices, Inc., ad5669rbruz Datasheet - Page 8

• Manufacturer Part Number: ad5669rbruz
• Description: Octal, 12-/16-bit Dac, I C , 5ppm/
• Manufacturer: Analog Devices, Inc.

AD5629R/AD5669R
I2C TIMING CHARACTERISTICS
V
Table 4.
1
2
The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior
of the part.
Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode, or less than 10 ns for high speed mode.
DD
= 2.7 V to 5.5 V; all specifications T
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SCL
1
2
3
4
5
6
7
8
9
10
11
11A
12
13
14
15
SP
2
1
Conditions
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Fast mode
MIN
to T
MAX
, f
SCL
= 400 kHz, unless otherwise noted.
Rev. PrA | Page 8 of 33
Min
4
0.6
4.7
1.3
250
100
0
0
4.7
0.6
4
0.6
4.7
1.3
4
0.6
10
10
300
300
20
20
0
Max
100
400
3.45
0.9
1000
300
300
300
1000
300
1000
300
300
300
50
Unit
kHz
kHz
μs
μs
μs
μs
ns
ns
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Preliminary Technical Data
Description
Serial clock frequency
t
t
t
t
t
condition
t
t
start condition
t
t
t
t
t
repeated start condition and after an
acknowledge bit
t
LDAC pulse width low
Falling edge of ninth SCL clock pulse of
last byte of a valid write to LDAC falling
edge
CLR pulse width low
Pulse width of spike suppressed
HIGH
LOW
SU;DAT
HD;DAT
SU;STA
HD;STA
BUF
SU;STO
RDA
FDA
RCL
RCL1
FCL
, rise time of SCL signal
, fall time of SCL signal
, bus-free time between a stop and a
, rise time of SDA signal
, fall time of SDA signal
, SCL low time
, rise time of SCL signal after a
, SCL high time
, setup time for a repeated start
, setup time for a stop condition
, data setup time
, hold time (repeated) start condition
, data hold time