st62t62b STMicroelectronics, st62t62b Datasheet - Page 10

• Manufacturer Part Number: st62t62b
• Description: 8-bit Otp/eprom Mcus With A/d Converter, Auto-reload Timer And Eeprom
• Manufacturer: STMicroelectronics

10
ST62T52B ST62T62B/E62B
MEMORY MAP (Cont’d)
1.3.6
(DRBR)
Address: E8h — Write only
Bit 7-5 = These bits are not used
Bit 4 - DRBR4. This bit, when set, selects RAM
Page 2.
Bit 1-3. Not used
Bit 0. DRBR0. This bit, when set, selects EEP-
ROM page 0.
The selection of the bank is made by program-
ming the Data RAM Bank Switch register (DRBR
register) located at address E8h of the Data
Space according to Table 1. No more than one
bank should be set at a time.
The DRBR register can be addressed like a RAM
Data Space at the address E8h; nevertheless it is
a write only register that cannot be accessed with
single-bit operations. This register is used to se-
lect the desired 64-byte RAM bank of the Data
Space. The number of banks has to be loaded in
the DRBR register and the instruction has to point
to the selected location as if it was in bank 0 (from
00h address to 3Fh address).
This register is not cleared during the MCU initial-
ization, therefore it must be written before the first
access to the Data Space bank region. Refer to
10/68
7
-
Data
-
RAM/EEPROM
-
DRBR
4
-
Bank
-
-
Register
DRBR
0
0
the Data Space description for additional informa-
tion. The DRBR register is not modified when an
interrupt or a subroutine occurs.
Notes :
Care is required when handling the DRBR register
as it is write only. For this reason, it is not allowed
to change the DRBR contents while executing in-
terrupt service routine, as the service routine can-
not save and then restore its previous content. If it
is impossible to avoid the writing of this register in
interrupt service routine, an image of this register
must be saved in a RAM location, and each time
the program writes to DRBR it must write also to
the image register. The image register must be
written first, so if an interrupt occurs between the
two instructions the DRBR is not affected.
In DRBR Register, only 1 bit must be set. Other-
wise two or more pages are enabled in parallel,
producing errors.
Table 3. Data RAM Bank Register Set-up
DRBR
other
10h
00
01
02
08
Not Available
Not available
Not available
RAM Page 2
ST62T52B
Reserved
None
EEPROM page 0
Not Available
Not available
RAM Page 2
ST62T62B
Reserved
None