mg84fl54b Megawin Technology, mg84fl54b Datasheet - Page 30

• Manufacturer Part Number: mg84fl54b
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

11. Enhanced UART
11.1. Frame Error Detection
While the SMOD0 bit (in PCON, bit 6) is set, the hardware will set the FE bit (SCON.7) when an invalid stop bit
is detected. The FE bit is not cleared by valid frames but should be cleared by software.
SCON (Address=98H, Serial Port Control Register)
SM0/FE:
PCON (Address=87H, Power Control Register)
SMOD0: Clear to let SCON.7 function as ‘SM0’, and set to let SCON.7 function as ‘FE’.
11.2. Automatic Address Recognition
Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial
bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead
by eliminating the need for the software to examine every serial address which passes by the serial port. This
feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive
Interrupt flag (RI) will be automatically set when the received byte contains either the “Given” address or the
“Broadcast” address. The 9-bit mode requires that the 9th information bit is a 1 to indicate that the received
information is an address and not data. Automatic address recognition is shown in the following figure.
The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information
received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast
address.
Mode 0 is the Shift Register mode and SM2 is ignored.
Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more
slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the
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SM0/FE
SM0: Serial Port Mode bit0 (when SMOD0=0).
FE: Frame Error bit (when SMOD0=1).
SMOD
7
7
SMOD0
SM1
6
6
LVF1
SM2
5
5
REN
POF
MG84FL54B Data Sheet
4
4
GF1
TB8
3
3
RB8
GF0
2
2
PD
TI
1
1
IDL
RI
0
0
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