mg84fl54b Megawin Technology, mg84fl54b Datasheet - Page 44

• Manufacturer Part Number: mg84fl54b
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

SSIG: /SS is ignored
SPEN: SPI enable
DORD: SPI data order
MSTR: Master/Slave mode select
CPOL: SPI clock polarity select
CPHA: SPI clock phase select
SPR1-SPR0: SPI clock rate select (associated with SPR2, when in master mode)
SPSTAT (Address=84H, SPI Status Register)
SPIF: SPI transfer completion flag
When a serial transfer finishes, the SPIF bit is set and an interrupt is generated if SPI interrupt is enabled. If /SS
pin is driven low when SPI is in master mode with SSIG=0, SPIF will also be set to signal the “mode change”.
The SPIF is cleared in software by writing ‘1’ to this bit.
THRE (read-only): Transmit Holding Register (THR) Empty flag.
0: means the THR is “empty”.
This bit is cleared by hardware when the THR is empty. That means the data in THR is loaded (by H/W) into the
Output Shift Register to be transmitted, and now the user can write the next data byte to SPDAT for next
transmission.
1: means the THR is “not empty”.
This bit is set by hardware just when SPDAT is written by software.
SPR2: SPI clock rate select (associated with SPR1 and SPR0)
SPDAT (Address=86H, SPI Data Register)
SPDAT has two physical registers for writing to and reading from:
(1) For writing to: SPDAT is the THR containing data to be loaded into the output shift register for transmit.
(2) For reading from: SPDAT is the input shift register containing the received data.
44
(MSB)
SPIF
7
7
If SSIG=1, MSTR decides whether the device is a master or slave.
If SSIG=0, the /SS pin decides whether the device is a master or slave.
If SPEN=1, the SPI is enabled.
If SPEN=0, the SPI interface is disabled and all SPI pins will be general-purpose I/O ports.
1: The LSB of the data byte is transmitted first.
0: The MSB of the data byte is transmitted first.
1: SPICLK is high when idle. The leading edge of SPICLK is the falling edge and the trailing edge is the
0: SPICLK is low when idle. The leading edge of SPICLK is the rising edge and the trailing edge is the
1: Data is driven on the leading edge of SPICLK, and is sampled on the trailing edge.
0: Data is driven when /SS pin is low (SSIG=0) and changes on the trailing edge of SPICLK. Data is
{SPR2,SPR1,SPR0} = 000: Fosc/3
(Note : If SSIG=1, CPHA must not be 1, otherwise the operation is not defined.)
falling edge.
sampled on the leading edge of SPICLK.
rising edge.
THRE
6
6
5
5
-
001: Fosc/6
010: Fosc/8
011: Fosc/12
MG84FL54B Data Sheet
4
4
-
100: Fosc/16
101: Fosc/24
110: Fosc/48
111: Fosc/96
3
3
-
(Where, Fosc is the system clock.)
2
2
-
1
1
-
SPR2
(LSB)
0
0
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