mg84fl54b Megawin Technology, mg84fl54b Datasheet - Page 72

• Manufacturer Part Number: mg84fl54b
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

Bit1: URXD0-- USB Receive Done Flag for endpoint 0.
Bit0: UTXD0-- USB Transmit Done Flag for endpoint 0.
UIE1 (USB Interrupt Enable Register 1, Address=DCH, SYS/USB_reset=xxxx-xx00, Read/Write)
Bit7~2: Reserved, always write 0.
Bit1: URXIE3-- USB Function Receive Interrupt Enable 3.
Bit0: UTXIE3-- USB Function Transmit Interrupt Enable 3.
UIFLG1 (USB Interrupt Flag Register 1, Address=DDH, SYS/USB_reset=xxxx-xx00, Read/Write)
Bit7~2: Reserve.
Bit1: URXD3-- USB Receive Done Flag for endpoint 3.
Bit0: UTXD3-- USB Transmit Done Flag for endpoint 3.
EPINDEX (Endpoint Index Register, Address=F1H, SYS/USB_reset=xxxx-x000, Read/Write)
Bit7~2: Reserved, always write 0.
Bit1~0: EPINX[1:0]-- Endpoint Index Bits [1:0]
EPCON (Endpoint Control Register, Endpoint-Indexed, Address=E1H, SYS/USB_reset=0000-0000, Read/Write)
Bit7: RXSTL-- Receive Endpoint Stall.
Bit6: TXSTL-- Transmit Endpoint Stall.
Bit5: RXDBM-- Receive Endpoint Double Buffer Mode.
72
RXSTL
7
7
7
This bit is set by hardware when detected a receive done on endpoint 0. UC can read/write-clear on this bit.
This bit is cleared when firmware writes '1' to it.
This bit is set by hardware when detected a transmit done on endpoint 0. UC can read/write-clear on this
bit. This bit is cleared when firmware writes '1' to it.
If this bit is set, enables the receive done interrupt for USB endpoint 3 (URXD3). Default is cleared.
If this bit is set, enables the transmit done interrupt for USB endpoint 3 (UTXD3). Default is cleared.
This bit is set by hardware when detected a receive done on endpoint 3. UC can read/write-clear on this bit.
This bit is cleared when firmware writes '1' to it. This bit is invalid only if DCON.EP3DIR is set.
This bit is set by hardware when detected a transmit done on endpoint 3. UC can read/write-clear on this
bit. This bit is cleared when firmware writes '1' to it. This bit is invalid only if DCON.EP3DIR is unset.
2’b00: Function Endpoint 0.
2’b01: Function Endpoint 1.
2’b10: Function Endpoint 2.
2’b11: Function Endpoint 3.
Set this bit to stall the receive endpoint.
Set this bit to stall the transmit endpoint.
Set this bit to enable the double buffer transfer for OUT transaction. Default is cleared.
This bit is only valid for endpoint 3 receive mode.
-
-
7
-
TXSTL
6
6
6
-
-
6
-
RXDBM
5
5
5
-
-
5
-
TXDBM
MG84FL54B Data Sheet
4
4
4
-
-
4
-
RXISO
3
3
3
-
-
3
-
RXEPEN
2
2
2
-
-
2
-
URXIE3
EPINX1
TXISO
1
1
1
URXD3
1
TXEPEN
UTXIE3
EPINX0
0
0
0
UTXD3
0
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