s29gl128n Meet Spansion Inc., s29gl128n Datasheet - Page 15

• Manufacturer Part Number: s29gl128n
• Description: 3.0 Volt-only Page Mode Flash Memory Featuring 110 Nm Mirrorbit ?rocess Technology
• Manufacturer: Meet Spansion Inc.

Device Bus Operations
Legend: L = Logic Low = V
Address, A
Notes:
1. Addresses are AMax:A0 in word mode; A
2. If WP# = V
3. D
S29GL-N_00_B3 October 13, 2006
Read
Write (Program/Erase)
Accelerated Program
Standby
Output Disable
Reset
unprotected as determined by the method described in “Write Protect (WP# )”. All sectors are unprotected when
shipped from the factory (The Secured Silicon Sector may be factory protected depending on version ordered.)
and
IN
or D
Figure
Word/Byte Configuration
VersatileI O
Operation
IN
OUT
= Address In, D
5).
IL
as required by command sequence, data polling, or sector protect algorithm (see
, the first or last sector group remains protected. If WP# = V
This section describes the requirements and use of the device bus operations, which are ini-
tiated through the internal command register. The command register itself does not occupy
any addressable memory location. The register is a latch used to store the commands, along
with the address and data information needed to execute the command. The contents of the
register serve as inputs to the internal state machine. The state machine outputs dictate the
function of the device.
they require, and the resulting output. The following subsections describe each of these op-
erations in further detail.
The BYTE# pin controls whether the device data I/ O pins operate in the byte or word config-
uration. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ0–DQ15 are
active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/ O pins
DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are
tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
The VersatileIO
vice generates and tolerates on CE# and DQ I/ Os to the same voltage level that is asserted
on V
For example, a V
receiving signals to and from other 1.8 or 3 V devices on the same data bus.
IO
. See Ordering Information for V
TM
IL
V
0.3 V
CE#
CC
, H = Logic High = V
IN
L
L
L
X
L
(V
±
= Data In, D
IO
TM
I/O
OE#
) Control
H
H
X
H
X
L
(V
D a t a
of 1.65–3.6 volts allows for I/ O at the 1.8 or 3 volt levels, driving and
IO
Table 1. Device Bus Operations
) control allows the host system to set the voltage levels that the de-
Table 1
WE# RESET#
S29GL-N MirrorBit™ Flash Family
H
X
H
X
L
L
OUT
Max
: A-1 in byte mode. Sector addresses are A
IH
= Data Out
V
S h e e t
0.3 V
lists the device bus operations, the inputs and control levels
, V
CC
H
H
H
H
L
ID
±
= 11.5–12.5 V, V
IO
WP#/ACC
Note 2
options on this device.
V
X
H
X
X
HH
Addresses
HH
(Note 1)
A
A
A
= 11.5–12.5V, X = Don’t Care, SA = Sector
X
X
X
IN
IN
IN
IH
, the first or last sector is protected or
(Note 3)
(Note 3)
High-Z
High-Z
High-Z
DQ0–
D
DQ7
OUT
Max
:A16 in both modes.
BYTE#
High-Z
High-Z
High-Z
(Note
(Note
= V
D
3)
3)
OUT
Figure
IH
DQ8–DQ15
DQ15 = A-1
DQ8–DQ14
2,
= High-Z,
High-Z
High-Z
High-Z
BYTE#
Figure
= V
IL
4,
13