s29ns01gr Meet Spansion Inc., s29ns01gr Datasheet - Page 25

• Manufacturer Part Number: s29ns01gr
• Description: S29ns01gr 1gb 64 M X 16 Bit , 1.8 V Burst Simultaneous Read/write, Multiplexed Mirrorbit Flash Memory
• Manufacturer: Meet Spansion Inc.

7.3
May 9, 2008 S29NS-R_00_03
Synchronous (Burst) Read Mode and Configuration Register
The device is capable of continuous sequential burst operation and linear burst operation of a preset length.
In order to use Synchronous (Burst) Read Mode the configuration register bit 15 must be set to 0.
Prior to entering burst mode, the system should determine how many wait states are needed for the initial
word of each burst access (see table below), what mode of burst operation is desired, how the RDY signal
transitions with valid data, and output drive strength. The system would then write the configuration register
command sequence. See
When the appropriate number of Wait States have occurred, data is output after the rising edge of the CLK.
Subsequent words are output t
increments the internal address counter. RDY indicates the initial latency and any subsequent waits.
The device has a fixed internal address boundary that occurs every 128 words. When crossing a boundary,
one or two additional wait states are required. The time the device is outputting data with the starting burst
address not divisible by eight, additional waits might be required.
The following Tables show the latency for variable wait state operation (note that ws = wait state).
Word
Word
D a t a
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
10 -13 wait states
S h e e t
9 wait states
Initial Wait
Initial Wait
Wait State
( A d v a n c e
Configuration Register on page 29
10
3
4
5
6
7
8
9
Table 7.3 Address Latency for 10 -13 Wait States
S29NS-R MirrorBit
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
BACC
Table 7.4 Address Latency for 9 Wait States
after the rising edge of each successive clock cycle, which automatically
Table 7.2 Wait State vs. Frequency
1 ws
1 ws
D1
D2
D3
D4
D5
D6
D7
D1
D2
D3
D4
D5
D6
D7
I n f o r m a t i o n )
1 ws
1 ws
1 ws
1 ws
D2
D3
D4
D5
D6
D7
D2
D3
D4
D5
D6
D7
®
Subsequent Clock Cycles After Initial Wait States
Subsequent Clock Cycles After Initial Wait States
Flash Family
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
D3
D4
D5
D6
D7
D3
D4
D5
D6
D7
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
for further details.
D4
D5
D6
D7
D4
D5
D6
D7
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
Frequency (Maximum MHz)
D5
D6
D7
D5
D6
D7
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
D6
D7
D6
D7
104
120
27
40
54
66
80
95
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
D7
D7
+2 ws
+2 ws
+2 ws
+2 ws
+2 ws
+2 ws
+2 ws
+2 ws
+1 ws
+1 ws
+1 ws
+1 ws
+1 ws
+1 ws
+1 ws
+1 ws
D8
D8
D8
D8
D8
D8
D8
D8
D8
D8
D8
D8
D8
D8
D8
D8
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