s29ns01gr Meet Spansion Inc., s29ns01gr Datasheet - Page 35

• Manufacturer Part Number: s29ns01gr
• Description: S29ns01gr 1gb 64 M X 16 Bit , 1.8 V Burst Simultaneous Read/write, Multiplexed Mirrorbit Flash Memory
• Manufacturer: Meet Spansion Inc.

7.7
7.8
May 9, 2008 S29NS-R_00_03
Writing Commands/Command Sequences
Program/Erase Operations
The device accepts Asynchronous write bus operations. During an asynchronous write bus operation, the
system must drive CE# and WE# to V
an address, AVD# must be driven to V
rising edge of AVD#, while data is latched on the 1st rising edge of WE#. See the
Operations on page 24
device. Each write is a command or part of a command sequence to the device. The address provided in
each write operation may be a bit pattern used to help identify the write as a command to the device. The
upper portion of the address may also select the bank or sector the command operation is to be performed. A
Bank Address (BA) is the set of address bits required to uniquely select a bank. Similarly, a Sector Address
(SA) is the address bits required to uniquely select a sector. The data in each write identifies the command
operation to be performed or supplies information needed to perform the operation. See
Command Definitions on page 60
Characteristics on page 48
operation.
For any program and/or erase operations, including writing command sequences, the system must drive
AVD# and CE# to V
V
Addresses are latched on the first falling edge of WE# or rising edge of AVD# during asynchronous writes.
Data is latched on the rising edge of WE# during asynchronous writes.
Note the following:
.
IL
When the Embedded Program algorithm is complete, the device returns to the calling routing (Erase
Suspend, SSR Lock, Secure Silicon Region, or Idle State).
The system can determine the status of the program operation by reading the Status Register. Refer to
Status Register on page 31
A 0 cannot be programmed back to a 1. A succeeding read shows that the data is still 0. Only erase
operations can convert a 0 to a 1
Any commands written to the device during the Embedded Program Algorithm are ignored except the
Reads from the non-Programming Bank, Program Suspend, and Status Read command. Any commands
written to the device during the Embedded Erase Algorithm are ignored except Reads from the non-
Erasing Bank, Erase Suspend and Status Read command.
A hardware reset immediately terminates the program/erase operation and the program command
sequence should be reinitiated once the device has returned to the idle state, to ensure data integrity.
, and OE# to V
D a t a
new data
old data
results
S h e e t
IH
IL
when writing commands or programming data.
0011
0101
0001
, and OE# to V
for the signal combinations that define each phase of a write bus operation to the
( A d v a n c e
represents the active current specification for a write (Embedded Algorithm)
S29NS-R MirrorBit
for information on these status bits.
for a listing of the commands accepted by the device. I
IH
IL
IL
when providing an address to the device, and drive WE# and CE# to
and OE# to V
. Addresses are latched on the first falling edge of WE# or on the
I n f o r m a t i o n )
®
Flash Family
IH
when providing an address and data. When latching
Table 7.1, Device Bus
Table 11.1,
CC2
in
DC
35