s29ns01gr Meet Spansion Inc., s29ns01gr Datasheet - Page 55

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s29ns01gr

Manufacturer Part Number
s29ns01gr
Description
S29ns01gr 1gb 64 M X 16 Bit , 1.8 V Burst Simultaneous Read/write, Multiplexed Mirrorbit Flash Memory
Manufacturer
Meet Spansion Inc.
Datasheet
May 9, 2008 S29NS-R_00_03
10.8.4
Hardware Reset (Reset#)
Notes
1. RDY active with data (CR.8 = 0 in the Configuration Register).
2. RDY active one clock cycle before data (CR.8 = 1 in the Configuration Register).
3. Figure shows the device not crossing a bank in the process of performing an erase or program.
D a t a
JEDEC
(Note 1)
(Note 2)
Address
AVD#
OE#,
(hex)
Data
RDY
RDY
CLK
CE#
CE#, OE#
RESET#
S h e e t
Parameter
(stays high)
(stays low)
7C
D124
t
Std
t
t
RPH
( A d v a n c e
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
RP
RH
7D
S29NS-R MirrorBit
Figure 10.11 Latency with Boundary Crossing
Address boundary occurs every 128 words, beginning at address
D125
RESET# Low to CE#
7E
t
RP
Reset High Time
RESET# Pulse
t
Figure 10.10 Reset Timings
RACC
Before Read
Table 10.2 Warm-Reset
D126
Width
t
Low
RPH
I n f o r m a t i o n )
7F
®
Flash Family
t
Description
RACC
latency
t
RH
D127
7F
t
latency
RACC
Min
Min
Min
80
t
RACC
D128
81
All Speed Options
200
50
10
D129
82
D130
83
Unit
ns
ns
us
55

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