s29jl064j Meet Spansion Inc., s29jl064j Datasheet - Page 41

• Manufacturer Part Number: s29jl064j
• Description: 64 Megabit 8m X 8-bit/4m X 16-bit Cmos 3.0 Volt-only, Simultaneous Read/write Flash Memory
• Manufacturer: Meet Spansion Inc.

11.5
11.6
11.7
April 7, 2011 S29JL064J_00_03
Reading Toggle Bits DQ6/DQ2
DQ5: Exceeded Timing Limits
DQ3: Sector Erase Timer
Refer to
toggle bit status, it must read DQ15–DQ0 (or DQ7–DQ0 for x8-only device) at least twice in a row to
determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle
bit after the first read. After the second read, the system would compare the new value of the toggle bit with
the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system
can read array data on DQ15–DQ0 (or DQ7–DQ0 for x8-only device) on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or
erase operation. If it is still toggling, the device did not completed the operation successfully, and the system
must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algorithm when it returns to
determine the status of the operation (top of
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a 1, indicating that the program or erase cycle was not successfully
completed.
The device may output a 1 on DQ5 if the system tries to program a 1 to a location that was previously
programmed to 0. Only an erase operation can change a 0 back to a 1. Under this condition, the device
halts the operation, and when the timing limit has been exceeded, DQ5 produces a 1.
Under both these conditions, the system must write the reset command to return to the read mode (or to the
erase-suspend-read mode if a bank was previously in the erase-suspend-program mode).
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors
are selected for erasure, the entire time-out also applies after each additional sector erase command. When
the time-out period is complete, DQ3 switches from a 0 to a 1. If the time between additional sector erase
commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See
also
After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is
1, the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until
the erase operation is complete. If DQ3 is 0, the device will accept additional sector erase commands. To
ensure the command has been accepted, the system software should check the status of DQ3 prior to and
following each subsequent sector erase command. If DQ3 is high on the second status check, the last
command might not have been accepted. The RDY/BSY# pin will be in the BUSY state under this condition.
Table 11.1 on page 42
Sector Erase Command Sequence on page
Figure 11.2 on page 40
shows the status of DQ3 relative to the other status bits.
D a t a
for the following discussion. Whenever the system initially begins reading
S h e e t
S29JL064J
Figure 11.2 on page
34.
40).
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