s908gr32ag3vfa Freescale Semiconductor, Inc, s908gr32ag3vfa Datasheet - Page 143

• Manufacturer Part Number: s908gr32ag3vfa
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

T1CH1 and T1CH0 — Timer 1 Channel I/O Bits
SPSCK — SPI Serial Clock
MOSI — Master Out/Slave In
MISO — Master In/Slave Out
SS — Slave Select
Data direction register D (DDRD) does not affect the data direction of port D pins that are being used by
the SPI module. However, the DDRD bits always determine whether reading port D returns the states of
the latches or the states of the pins. See
12.6.2 Data Direction Register D
Data direction register D (DDRD) determines whether each port D pin is an input or an output. Writing a
1 to a DDRD bit enables the output buffer for the corresponding port D pin; a 0 disables the output buffer.
DDRD7–DDRD0 — Data Direction Register D Bits
Figure 12-15
Freescale Semiconductor
The PTD7/T1CH1–PTD6/T1CH0 pins are the TIM1 input capture/output compare pins. The edge/level
select bits, ELSxB and ELSxA, determine whether the PTD7/T1CH1–PTD6/T1CH0 pins are timer
channel I/O pins or general-purpose I/O pins. See
Chapter 18 Timer Interface Module
The PTD3/SPSCK pin is the serial clock input of the SPI module. When the SPE bit is clear, the
PTD3/SPSCK pin is available for general-purpose I/O.
The PTD2/MOSI pin is the master out/slave in terminal of the SPI module. When the SPE bit is clear,
the PTD2/MOSI pin is available for general-purpose I/O.
The PTD1/MISO pin is the master in/slave out terminal of the SPI module. When the SPI enable bit,
SPE, is clear, the SPI module is disabled, and the PTD1/MISO pin is available for general-purpose I/O.
The PTD0/SS pin is the slave select input of the SPI module. When the SPE bit is clear, or when the
SPI master bit, SPMSTR, is set, the PTD0/SS pin is available for general-purpose I/O. When the SPI
is enabled, the DDRD0 bit in data direction register D (DDRD) has no effect on the PTD0/SS pin.
These read/write bits control port D data direction. Reset clears DDRD7–DDRD0, configuring all port
D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
shows the port D I/O logic.
Address:
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Reset:
Read:
Write:
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
DDRD7
$0007
Bit 7
0
Figure 12-14. Data Direction Register D (DDRD)
DDRD6
6
0
(TIM2).
DDRD5
Table
5
0
12-5.
NOTE
DDRD4
4
0
Chapter 17 Timer Interface Module (TIM1)
DDRD3
3
0
DDRD2
2
0
DDRD1
1
0
DDRD0
Bit 0
0
and
Port D
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