s908gr32ag3vfa Freescale Semiconductor, Inc, s908gr32ag3vfa Datasheet - Page 80

• Manufacturer Part Number: s908gr32ag3vfa
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Clock Generator Module (CGM)
4.4.9 CGM Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal goes to the SIM, which generates the MCU clocks.
CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency. CGMOUT is software
programmable to be either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK,
divided by two.
4.4.10 CGM CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
4.5 CGM Registers
These registers control and monitor operation of the CGM:
Figure 4-3
80
NOTES:
Addr.
$003A
$003B
$0036
$0037
$0038
$0039
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
•
•
•
•
•
PLL control register (PCTL) — see
PLL bandwidth control register (PBWC) — see
PLL multiplier select register high (PMSH) — see
PLL multiplier select register low (PMSL) — see
PLL VCO range select register (PMRS) — see
PLL Multiplier Select High
PLL Multiplier Select Low
PLL VCO Select Range
is a summary of the CGM registers.
PLL Bandwidth Control
Register Name
PLL Control Register
Reserved Register
Register (PBWC)
Register (PMSH)
Register (PMRS)
Register (PMSL)
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
See page 81.
See page 82.
See page 83.
See page 84.
See page 84.
(PCTL)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Figure 4-3. CGM I/O Register Summary
PLLIE
AUTO
MUL7
VRS7
Bit 7
0
0
0
0
0
0
0
0
= Unimplemented
4.5.1 PLL Control Register
LOCK
MUL6
VRS6
PLLF
6
0
0
0
0
1
1
0
0
PLLON
MUL5
VRS5
ACQ
4.5.5 PLL VCO Range Select Register
4.5.2 PLL Bandwidth Control Register
5
1
0
0
0
0
0
0
0
4.5.4 PLL Multiplier Select Register Low
4.5.3 PLL Multiplier Select Register High
MUL4
VRS4
BCS
R
4
0
0
0
0
0
0
0
0
0
= Reserved
MUL11
MUL3
VRS3
R
R
3
0
0
0
0
0
0
0
MUL10
MUL2
VRS2
R
R
2
0
0
0
0
0
0
0
Freescale Semiconductor
VPR1
MUL9
MUL1
VRS1
R
1
0
0
0
0
0
0
0
VPR0
MUL8
MUL0
VRS0
Bit 0
R
R
0
0
0
0
0
1