s908gr32ag3vfa Freescale Semiconductor, Inc, s908gr32ag3vfa Datasheet - Page 174

• Manufacturer Part Number: s908gr32ag3vfa
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Enhanced Serial Communications Interface (ESCI) Module
13.8.7 ESCI Baud Rate Register
The ESCI baud rate register (SCBR) together with the ESCI prescaler register selects the baud rate for
both the receiver and the transmitter.
LINT — LIN Transmit Enable
LINR — LIN Receiver Bits
174
This read/write bit selects the enhanced ESCI features for the local interconnect network (LIN) protocol
as shown in
This read/write bit selects the enhanced ESCI features for the local interconnect network (LIN) protocol
as shown in
In LIN (version 1.2) systems, the master node transmits a break character which will appear as
11.05–14.95 dominant bits to the slave node. A data character of 0x00 sent from the master might
appear as 7.65–10.35 dominant bit times. This is due to the oscillator tolerance requirement that the
slave node must be within ±15% of the master node's oscillator. Since a slave node cannot know if it
is running faster or slower than the master node (prior to synchronization), the LINR bit allows the slave
node to differentiate between a 0x00 character of 10.35 bits and a break character of 11.05 bits. The
break symbol length must be verified in software in any case, but the LINR bit serves as a filter,
preventing false detections of break characters that are really 0x00 data characters.
Address:
There are two prescalers available to adjust the baud rate. One in the ESCI
baud rate register and one in the ESCI prescaler register.
Table
Table
Reset:
Read:
Write:
LINT
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
0
0
0
1
1
1
1
13-6. Reset clears LINT.
13-6. Reset clears LINR.
$0019
LINT
Bit 7
R
0
LINR
0
1
1
0
0
1
1
Figure 13-17. ESCI Baud Rate Register (SCBR)
= Reserved
LINR
6
0
M
Table 13-6. ESCI LIN Control Bits
X
0
1
0
1
0
1
Normal ESCI functionality
11-bit break detect enabled for LIN receiver
12-bit break detect enabled for LIN receiver
13-bit generation enabled for LIN transmitter
14-bit generation enabled for LIN transmitter
11-bit break detect/13-bit generation enabled for LIN
12-bit break detect/14-bit generation enabled for LIN
SCP1
5
0
NOTE
SCP0
4
0
Functionality
R
3
0
SCR2
2
0
SCR1
1
0
Freescale Semiconductor
SCR0
Bit 0
0