cy7c1380d-250bzxi Cypress Semiconductor Corporation., cy7c1380d-250bzxi Datasheet - Page 20

• Manufacturer Part Number: cy7c1380d-250bzxi
• Description: 18-mbit 512k X 36/1m X 18 Pipelined Sram
• Manufacturer: Cypress Semiconductor Corporation.

Switching Characteristics
Document #: 38-05543 Rev. *E
Notes:
t
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
Setup Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
20. Timing reference level is 1.5V when V
21. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
22. This part has a voltage regulator internally; t
23. t
24. At any given voltage and temperature, t
25. This parameter is sampled and not 100% tested.
POWER
CYC
CH
CL
CO
DOH
CLZ
CHZ
OEV
OELZ
OEHZ
AS
ADS
ADVS
WES
DS
CES
AH
ADH
ADVH
WEH
DH
CEH
Parameter
can be initiated.
mV from steady-state voltage.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
CHZ
, t
CLZ
,t
OELZ
, and t
V
Clock Cycle Time
Clock HIGH
Clock LOW
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z
Clock to High-Z
OE LOW to Output Valid
OE LOW to Output Low-Z
OE HIGH to Output High-Z
Address Setup Before CLK Rise
ADSC, ADSP Setup Before CLK Rise
ADV Setup Before CLK Rise
GW, BWE, BW
Data Input Setup Before CLK Rise
Chip Enable SetUp Before CLK Rise
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
ADV Hold After CLK Rise
GW, BWE, BW
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
OEHZ
DD
(Typical) to the first Access
are specified with AC test conditions shown in part (b) of
DDQ
OEHZ
X
X
Description
Over the Operating Range
[23, 24, 25]
[23, 24, 25]
Setup Before CLK Rise
Hold After CLK Rise
= 3.3V and is 1.25V when V
POWER
is less than t
is the time that the power needs to be supplied above V
[23, 24, 25]
[23, 24, 25]
OELZ
[22]
and t
CHZ
DDQ
is less than t
[20, 21]
= 2.5V.
Min.
4.0
1.7
1.7
1.0
1.0
1.2
1.2
1.2
1.2
1.2
1.2
0.3
0.3
0.3
0.3
0.3
0.3
1
0
250 MHz
AC Test Loads and Waveforms on page
CLZ
to eliminate bus contention between SRAMs when sharing the same
Max.
2.6
2.6
2.6
2.6
Min.
2.0
2.0
1.3
1.3
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
200 MHz
1
5
0
DD
(minimum) initially before a read or write operation
Max.
3.0
3.0
3.0
3.0
Min.
2.2
2.2
1.3
1.3
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
19. Transition is measured ± 200
167 MHz
1
6
0
Max.
3.4
3.4
3.4
3.4
Page 20 of 30
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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