cy7c1380d-250bzxi Cypress Semiconductor Corporation., cy7c1380d-250bzxi Datasheet - Page 6

• Manufacturer Part Number: cy7c1380d-250bzxi
• Description: 18-mbit 512k X 36/1m X 18 Pipelined Sram
• Manufacturer: Cypress Semiconductor Corporation.

Pin Definitions
Document #: 38-05543 Rev. *E
A
BW
BW
GW
BWE
CLK
CE
CE
CE
OE
ADV
ADSP
ADSC
ZZ
DQs, DQP
V
0
DD
, A
1
2
3
A
C
Name
[2]
[2]
, BW
, BW
1
, A
B
D
X
Asynchronous
Asynchronous
Power Supply Power supply inputs to the core of the device.
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Clock
IO-
IO
Address inputs used to select one of the address locations. Sampled at the rising edge of
the CLK if ADSP or ADSC is active LOW, and CE
are fed to the two-bit counter. .
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (all bytes are written, regardless of the values on BW
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
only when a new external address is loaded.
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
address is loaded.
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
is loaded.
Output enable, asynchronous input, active LOW. Controls the direction of the IO pins. When
LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
Advance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst cycle.
Address strobe from processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A1: A0
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized. ASDP is ignored when CE
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A1: A0
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized.
ZZ sleep input. This active HIGH input places the device in a non-time critical sleep condition
with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull down.
Bidirectional data IO lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQP
2
1
and CE
and CE
1
and CE
2
3
to select or deselect the device. CE
to select or deselect the device. ADSP is ignored if CE
3
to select or deselect the device. CE
X
are placed in a tri-state condition.
1
is deasserted HIGH.
Description
3
1
is sampled only when a new external address
, CE
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
2
2
, and CE
is sampled only when a new external
3
[2]
are sampled active. A1: A0
1
is HIGH. CE
X
and BWE).
1
Page 6 of 30
is sampled
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