cy7c1380d-250bzxi Cypress Semiconductor Corporation., cy7c1380d-250bzxi Datasheet - Page 7

• Manufacturer Part Number: cy7c1380d-250bzxi
• Description: 18-mbit 512k X 36/1m X 18 Pipelined Sram
• Manufacturer: Cypress Semiconductor Corporation.

Pin Definitions
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (t
MHz device).
The
supports secondary cache in systems utilizing a linear or
interleaved burst sequence. The interleaved burst order
supports Pentium
sequence is suited for processors that utilize a linear burst
sequence. The burst order is user selectable, and is
determined by sampling the MODE input. Accesses can be
initiated with either the processor address strobe (ADSP) or
the controller address strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BW
enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous chip selects (CE
asynchronous output enable (OE) provide for easy bank
Document #: 38-05543 Rev. *E
V
V
V
MODE
TDO
TDI
TMS
TCK
NC
SS
SSQ
DDQ
Name
CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
Synchronous
Synchronous
Synchronous
JTAG serial
JTAG serial
Input-Static
JTAG serial
®
IO Ground
IO Power
Ground
(continued)
Supply
and i486™ processors. The linear burst
JTAG-
output
Clock
input
input
IO
–
Ground for the core of the device.
Ground for the IO circuitry.
Power supply for the IO circuitry.
Selects burst order. When tied to GND selects linear burst sequence. When tied to V
floating selects interleaved burst sequence. This is a strap pin and must remain static during
device operation. Mode pin has an internal pull up.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG
feature is not being utilized, this pin must be disconnected. This pin is not available on TQFP
packages.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is
not being utilized, this pin can be disconnected or connected to V
TQFP packages.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is
not being utilized, this pin can be disconnected or connected to V
TQFP packages.
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be
connected to V
No Connects. 36M, 72M, 144M, 288M, 576M and 1G are address expansion pins and are not
internally connected to the die.
X
) inputs. A global write
1
, CE
CO
2
, CE
) is 2.6 ns (250
SS
. This pin is not available on TQFP packages.
3
) and an
selection and output tri-state control. ADSP is ignored if CE
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) CE
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE
is stored into the address advancement logic and the address
register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
output registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 2.6 ns (250 MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always tri-stated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE
signal. Consecutive single read cycles are supported. Once
the SRAM is deselected at clock rise by the chip select and
either ADSP or ADSC signals, its output will tri-state
immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE
1
is HIGH. The address presented to the address inputs (A)
1
1
Description
, CE
, CE
2
2
, CE
, CE
3
3
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
are all asserted active, and (3) the write
are all asserted active. The address
DD
DD
. This pin is not available on
. This pin is not available on
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or left
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