cy7c1380d-250bzxi Cypress Semiconductor Corporation., cy7c1380d-250bzxi Datasheet - Page 8

• Manufacturer Part Number: cy7c1380d-250bzxi
• Description: 18-mbit 512k X 36/1m X 18 Pipelined Sram
• Manufacturer: Cypress Semiconductor Corporation.

presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The write signals (GW, BWE, and BW
ADV inputs are ignored during this first cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the
corresponding address location in the memory array. If GW is
HIGH, then the write operation is controlled by BWE and BW
signals.
The
provides byte write capability that is described in the write
cycle descriptions table. Asserting the byte write enable input
(BWE) with the selected byte write (BW
write to only the desired bytes. Bytes not selected during a
byte write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations.
The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F is a
common IO device, the output enable (OE) must be deserted
HIGH before presenting data to the DQs inputs. Doing so will
tri-state the output drivers. As a safety precaution, DQs are
automatically tri-stated whenever a write cycle is detected,
regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following
conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP
is deserted HIGH, (3) CE
and (4) the appropriate combination of the write inputs (GW,
BWE, and BW
desired byte(s). ADSC-triggered Write accesses require a
single clock cycle to complete. The address presented to A is
loaded
advancement logic while being delivered to the memory array.
The ADV input is ignored during this cycle. If a global write is
conducted, the data presented to the DQs is written into the
corresponding address location in the memory core. If a byte
write is conducted, only the selected bytes are written. Bytes
not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F is a
common IO device, the output enable (OE) must be deserted
HIGH before presenting data to the DQs inputs. Doing so will
tri-state the output drivers. As a safety precaution, DQs are
ZZ Mode Electrical Characteristics
Document #: 38-05543 Rev. *E
I
t
t
t
t
DDZZ
ZZS
ZZREC
ZZI
RZZI
Parameter
CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
into
X
the
) are asserted active to conduct a write to the
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to sleep current
ZZ Inactive to exit sleep current
address
1
, CE
2
register
, CE
Description
3
are all asserted active,
X
) input, will selectively
and
the
address
X
) and
X
ZZ > V
ZZ > V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
automatically tri-stated whenever a write cycle is detected,
regardless of the state of OE.
Burst Sequences
The
provides a two-bit wraparound counter, fed by A1: A0, that
implements an interleaved or a linear burst sequence. The
interleaved burst sequence is designed specifically to support
Intel Pentium applications. The linear burst sequence is
designed to support processors that follow a linear burst
sequence. The burst sequence is user selectable through the
MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation sleep mode. Two
clock cycles are required to enter into or exit from this sleep
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the sleep mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the sleep mode. CE
remain inactive for the duration of t
returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
Linear Burst Address Table (MODE = GND)
Address
Address
Test Conditions
DD
DD
A1: A0
A1: A0
First
First
00
01
10
11
00
01
10
11
– 0.2V
– 0.2V
CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
Address
Address
Second
Second
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
A1: A0
A1: A0
1
01
00
10
01
10
00
11
11
, CE
2
, CE
2t
Min.
CYC
0
3
Address
Address
, ADSP, and ADSC must
A1: A0
A1: A0
Third
Third
ZZREC
10
11
00
01
10
11
00
01
2t
2t
Max.
80
after the ZZ input
CYC
CYC
Page 8 of 30
Address
Address
Fourth
A1: A0
Fourth
A1: A0
10
01
00
00
01
10
11
11
Unit
mA
ns
ns
ns
ns
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