mt48h8m16lf Micron Semiconductor Products, mt48h8m16lf Datasheet
mt48h8m16lf
Available stocks
Related parts for mt48h8m16lf
mt48h8m16lf Summary of contents
Page 1
... Mobile SDRAM MT48H8M16LF – 2 Meg banks MT48H4M32LF – 1 Meg banks Features • 1.7–1.95V / DD DD • Fully synchronous; all signals registered on positive edge of system clock • Internal, pipelined operation; column address can be changed every clock cycle • ...
Page 2
Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
List of Figures Figure 1: Part Numbering ...
Page 4
List of Tables Table 1: Configuration Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
Figure 1: Part Numbering MT Micron Technology Product family 48 = Mobile SDR SDRAM Operating voltage H = 1.8V/1.8V Configuration 8 Meg Meg x 32 Addressing LF = Mobile standard addressing General Description The Micron memory containing ...
Page 6
Functional Block Diagrams Figure 2: 8 Meg x 16 SDRAM CKE CLK Control CS# logic WE# CAS# RAS# EXT mode register Refresh Mode register counter Address Address BA0, BA1 register PDF: 09005aef832ff1ea / Source: 09005aef832ff1ac 128mb_mobile_sdram_y35m__2.fm - Rev. B 6/08 ...
Page 7
Figure 3: 4 Meg x 32 SDRAM CKE CLK Control CS# logic WE# CAS# RAS# EXT mode register Refresh counter Mode register Address Address BA0, BA1 register PDF: 09005aef832ff1ea / Source: 09005aef832ff1ac 128mb_mobile_sdram_y35m__2.fm - Rev. B 6/08 EN 128Mb: 8 ...
Page 8
Ball Assignments Figure 4: 54-Ball VFBGA (Top View Notes: 1. The E2 pin must be connected to V PDF: 09005aef832ff1ea / Source: 09005aef832ff1ac 128mb_mobile_sdram_y35m__2.fm - Rev. B 6/08 EN 128Mb: 8 ...
Page 9
Figure 5: 90-Ball VFBGA (Top View Notes: 1. The K2 pin must be connected to V PDF: 09005aef832ff1ea / Source: 09005aef832ff1ac 128mb_mobile_sdram_y35m__2.fm - Rev. B ...
Page 10
Ball Descriptions Table 3: VFBGA Ball Descriptions 54-Ball VFBGA 90-Ball VFBGA F7, F8, F9 K7, J9, K8 E8, F1 K9, K1, F8, F2 G7, G8 J7, H8 H7, H8, J8, J7, G8, G9, F7, ...
Page 11
Table 3: VFBGA Ball Descriptions (continued) 54-Ball VFBGA 90-Ball VFBGA A7, B3, C7, D3 B2, B7, C9, D9, E1, L1, M9, N9, P2, P7 A3, B7, C3, D7 B8, B3, C1, D1, E9, L9, M1, N1, P3, P8 A9, E7, ...
Page 12
Package Dimensions Figure 6: 54-Ball VFBGA (8mm x 8mm) Seating plane A 0.1 A 54X Ø0.45 Dimensions apply 8 ±0.1 to solder balls post-reflow. Pre- reflow balls are Ø0.42 on Ø0.4 SMD ball pads. 3.2 6.4 0.8 ...
Page 13
Figure 7: 90-Ball VFBGA (8mm x 13mm) Seating plane A 0 ±0.1 90X 0.45 Dimensions apply to solder balls post- reflow. Pre-reflow balls are Ø0. Ø0.4 SMD ball pads. 5.6 11.2 0.8 TYP 3.2 ...
Page 14
Electrical Specifications Absolute Maximum Ratings Stresses greater than those listed in Table 4 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those ...
Page 15
Table 6: Capacitance Notes apply to all parameters and conditions Parameter Input capacitance: CLK Input capacitance: All other input-only balls Input/output capacitance: DQs Notes: 1. This parameter is sampled MHz. Table 7: I Specifications and Conditions ...
Page 16
Table 8: I Specifications and Conditions (x32) (continued) DD Note 1 applies to all parameters; notes appear on page 16; V Parameter/Condition Standby current: Active mode; CKE = HIGH; CS# = HIGH; All banks active after No accesses in progress ...
Page 17
Table 10: Electrical Characteristics and Recommended AC Operating Conditions Notes 1–5 apply to all parameters; notes appear on page 17 Parameter Access time from CLK (positive edge) Address hold time Address setup time CLK high-level width CLK low-level width Clock ...
Page 18
Table 11: AC Functional Characteristics (continued) Notes 1–5 apply to all parameters Parameter WRITE command to input data delay LOAD MODE REGISTER command to ACTIVE or REFRESH command CKE to clock enable or power-down exit mode Last data-in to PRECHARGE ...
Page 19
Table 12: Target Output Drive Characteristics (Full Strength) Notes 1–2 apply to all values. Characteristics are specified under best and worst process variations/conditions Pull-Down Current (mA) Voltage (V) Min 0.00 0.00 0.10 2.80 0.20 5.60 0.30 8.40 0.40 11.20 0.50 ...
Page 20
Table 13: Target Output Drive Characteristics (Three-Quarter Strength) Notes 1–3 apply to all values. Characteristics are specified under best and worst process variations/conditions. Voltage (V) Min 0.00 0.00 0.10 1.96 0.20 3.92 0.30 5.88 0.40 7.84 0.50 9.80 0.60 11.76 ...
Page 21
Table 14: Target Output Drive Characteristics (One-Half Strength) Notes 1–2 apply to all values. Characteristics are specified under best and worst process variations/conditions Voltage (V) Min 0.00 0.00 0.10 1.27 0.20 2.55 0.30 3.82 0.40 5.09 0.50 6.36 0.60 7.64 ...
Page 22
Functional Description Mobile SDRAMs are quad-bank DRAMs that operate at 1.8V and include a synchronous interface. All signals are registered on the positive edge of the clock signal, CLK. Read and write accesses to SDRAMs are burst oriented; accesses start ...
Page 23
Commands Table 15 provides a quick reference of available commands. A written description of each command follows the table. Three additional Truth Tables appear on pages 28–32; these tables provide current state/next state information. Table 15: Truth Table – Commands ...
Page 24
COMMAND INHIBIT The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO ...
Page 25
READ The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided selects the starting column location. The value on input A10 ...
Page 26
Figure 10: WRITE Command CLK CKE CS# RAS# CAS# WE# Address A10 BA0, BA1 Notes enable auto precharge, DIS AP = disable auto precharge PRECHARGE The PRECHARGE command is used to deactivate the open row in ...
Page 27
Figure 11: PRECHARGE Command CLK CKE CS# RAS# CAS# WE# Address A10 BA0, BA1 BURST TERMINATE The BURST TERMINATE command is used to either truncate fixed-length or continuous page bursts. The most recently registered READ or WRITE command prior to ...
Page 28
DEEP POWER-DOWN (DPD) The DEEP POWER-DOWN command causes the Mobile SDRAM to enter deep power- down mode. DPD is an operating mode used to achieve maximum power reduction by eliminating the power of the whole memory array of the devices. ...
Page 29
The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or supported commands to the other bank should be issued on any clock edge occurring during these states. Supported ...
Page 30
Table 17: Truth Table – Current State Bank n, Command to Bank m Notes 1–6; notes appear below this table Current State CS# RAS# CAS# Any Idle X X Row L L activating active, ...
Page 31
A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs to bank m ...
Page 32
Table 18: Truth Table – CKE Notes 1–4; notes appear below this table CKE CKE Current State n Power-down Self refresh Clock suspend Deep power-down L H Power-down Deep power-down Self refresh Clock suspend H L All ...
Page 33
When in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register powers unknown state, it should be ...
Page 34
Register Definition Mode Register There are two mode registers in the Mobile SDRAM component, the mode register and the extended mode register (EMR). The mode register is illustrated in Figure 13 on page 35. The mode register defines the specific ...
Page 35
Figure 13: Mode Register Definition BA1 BA0 An Mn+2 Mn+1 Mn n+2 n Reserved* Mn+2 Mn+1 Mode Register Definition 0 0 Base mode register 1 0 Reserved 1 0 Extended mode register 1 1 Reserved M9 Write ...
Page 36
A[8:1] when A[8:2] when and A[8:3] when The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Continuous page burst wraps within the page ...
Page 37
Figure 14: CAS Latency CLK Command CLK Command Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combi- nations of values for M7 and M8 are reserved for future use. Reserved states ...
Page 38
Figure 15: Extended Mode Register BA1 n+2 n Mode Register Definition Status register 1 0 Extended mode register 1 1 Reserved En ... E10 ...
Page 39
Half bank (bank 0; BA1 = BA0 = row address MSB = 0) 5. Quarter bank (bank 0; BA1 = BA0 = row address MSB - WRITE and READ commands occur to any bank selected during ...
Page 40
Timing Diagrams READs READ bursts are initiated with a READ command, as shown in Figure 9. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. ...
Page 41
Figure 17: Consecutive READ Bursts CLK Command Address DQ CLK Command Address DQ Notes: 1. Each READ command may be to any bank. DQM is LOW. PDF: 09005aef832ff1ea / Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr5.08__4.fm - Rev. B 6/08 EN 128Mb: 8 Meg ...
Page 42
Figure 18: Random READ Accesses CLK Command Address DQ CLK Command Address DQ Notes: 1. Each READ command can be to any bank. DQM is LOW. Data from any READ burst may be truncated with a subsequent WRITE command, and ...
Page 43
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 18 on page 42 shows the case where the clock frequency ...
Page 44
Figure 20: READ-to-WRITE with Extra Clock Cycle CLK DQM Command Address DQ Notes The READ command may be to any bank, and the WRITE command may be to any bank. Figure 21: READ-to-PRECHARGE Command Address Command ...
Page 45
Continuous-page READ bursts may be truncated with a BURST TERMINATE command and fixed -length READ bursts may be truncated with a BURST TERMINATE command, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles ...
Page 46
Figure 23: Alternating Bank Read Accesses CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM Row Address Enable auto ...
Page 47
Figure 24: READ Continuous Page Burst CLK CKS t CKH CKE t CMS t CMH Command ACTIVE NOP READ t CMS t CMH DQM Address Row ...
Page 48
Figure 25: READ – DQM Operation CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM Row Address Enable auto ...
Page 49
WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 10 on page 26. The starting column and bank addresses are provided with the WRITE command and auto precharge is either enabled or disabled for that access. ...
Page 50
Figure 27: WRITE-to-WRITE CLK Command Address DQ Notes: 1. DQM is LOW. Each WRITE command may be to any bank. Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed-length WRITE burst ...
Page 51
Figure 28: Random WRITE Cycles CLK Command Address DQ Notes: 1. Each WRITE command may be to any bank. DQM is LOW. Figure 29: WRITE-to-READ CLK Command Address Notes: 1. The WRITE command may be to any bank, and the ...
Page 52
Figure 30: WRITE-to-PRECHARGE t t WR@ DQM Command Address t t WR@ DQM Command Address Notes: 1. DQM could remain LOW in this example if the WRITE burst is a fixed length of two. Fixed-length WRITE bursts can be truncated ...
Page 53
Figure 31: Terminating a WRITE Burst CLK Command Address Notes: 1. DQM is LOW. Figure 32: Alternating Bank Write Accesses CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP ...
Page 54
Figure 33: WRITE – Continuous Page Burst CLK CKS t CKH CKE t CMS t CMH Command ACTIVE NOP DQM Address Row Row A10 t ...
Page 55
Figure 34: WRITE – DQM Operation CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP DQM Address Row Row A10 ...
Page 56
A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the continuous page burst mode, where auto precharge does not apply. In ...
Page 57
Figure 35: READ With Auto Precharge Interrupted by a READ CLK Command BANK n Internal states BANK m Address DQ Notes: 1. DQM is LOW. Figure 36: READ With Auto Precharge Interrupted by a WRITE CLK READ - AP Command ...
Page 58
Figure 37: READ – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM Row Address Enable ...
Page 59
Figure 38: READ – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM Address Row Row ...
Page 60
Figure 39: Single READ – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP DQM Row Address A10 Row t AS ...
Page 61
Figure 40: Single READ – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM Address Row ...
Page 62
Figure 41: WRITE With Auto Precharge Interrupted by a READ Command Internal States Bank m Address Notes: 1. DQM is LOW. Figure 42: WRITE With Auto Precharge Interrupted by a WRITE Command Internal States Address Notes: 1. DQM is LOW. ...
Page 63
Figure 43: WRITE – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP WRITE t CMS DQM Address Row Column m t ...
Page 64
Figure 44: WRITE – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP WRITE t CMS DQM Address Row Column m t ...
Page 65
Figure 45: Single WRITE – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM Address Row ...
Page 66
Figure 46: Single WRITE – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM Address Row ...
Page 67
Figure 47: Auto Refresh Mode T0 T1 CLK t CK CKE t CKS t CKH t CMS t CMH Command PRECHARGE NOP DQM Address All banks A10 Single bank BA0, BA1 Bank(s) High ...
Page 68
The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock ball) prior to CKE going back HIGH. After CKE ...
Page 69
CKE, for maximum power savings while in standby. The device may not remain in the power-down state longer than the refresh period (64ms) since no REFRESH operations are performed in this mode. ...
Page 70
Clock Suspend The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which ...
Page 71
Figure 51: Clock Suspend During READ Burst CLK CKE Internal clock Command Address DQ Notes: 1. For this example greater, and DQM is LOW. PDF: 09005aef832ff1ea / Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr5.08__4.fm - Rev. B ...
Page 72
Figure 52: Clock Suspend Mode CLK t CKS t CKH CKE t CKS t CKH t CMS t CMH Command READ NOP t CMS t CMH DQM Address Column m ...
Page 73
Revision History: Device Rev. B, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 74
Revision History: Commands, Operations, and Timing Diagrams Revision History: Commands, Operations, and Timing Diagrams Update . . . . . . . . . . . . . . . . . . . . . . . . . ...