mt46h8m16lfcf-75-it Micron Semiconductor Products, mt46h8m16lfcf-75-it Datasheet - Page 65
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mt46h8m16lfcf-75-it
Manufacturer Part Number
mt46h8m16lfcf-75-it
Description
128mb Mobile Ddr Sdram Mt46h4m32lfb5-6
Manufacturer
Micron Semiconductor Products
Datasheet
1.MT46H8M16LFCF-75-IT.pdf
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Figure 36:
PDF: 09005aef8331b3e9 / Source: 09005aef8331b3ce
ddr_mobile_sdram_cmd_op_timing_dia_fr5.08__3.fm - Rev. B 06/08 EN
Command
Address
Random WRITE Cycles
DQS
CK#
DM
DQ
CK
Notes:
WRITE
Bank,
Col b
1. D
2. b' (or x, n, a, g) = the next data-in following D
3. Programmed BL = 2, 4, 8, or 16 in cases shown.
4. Each WRITE command may be to any bank.
T0
t
burst order.
DQSS (NOM)
IN
b (or x, n, a, g) = data-in for column b (or x, n, q, g).
WRITE
Bank,
Col x
D
T1
b
IN
T1n
D
b’
IN
WRITE
Bank,
Col n
T2
D
x
IN
65
T2n
D
x’
IN
WRITE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Bank,
Col a
D
T3
128Mb: x16, x32 Mobile DDR SDRAM
n
IN
Don’t Care
T3n
IN
D
n’
IN
b (x, n, a, g) according to the programmed
WRITE
Bank,
T4
Col g
D
a
IN
T4n
D
a’
IN
Transitioning Data
©2007 Micron Technology, Inc. All rights reserved.
NOP
D
Timing Diagrams
T5
g
IN
T5n
D
g’
IN
Preliminary
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