mt46h8m16lfcf-75-it Micron Semiconductor Products, mt46h8m16lfcf-75-it Datasheet - Page 78

• Manufacturer Part Number: mt46h8m16lfcf-75-it
• Description: 128mb Mobile Ddr Sdram Mt46h4m32lfb5-6
• Manufacturer: Micron Semiconductor Products

Self Refresh
Figure 48:
PDF: 09005aef8331b3e9 / Source: 09005aef8331b3ce
ddr_mobile_sdram_cmd_op_timing_dia_fr5.08__3.fm - Rev. B 06/08 EN
Command
Address
Self Refresh Mode
CKE
DQS
CK#
DM
CK
DQ
1
1
4
Notes:
t
t
IS
IS
t
NOP
RP
T0
1. Clock must be stable, cycling within specifications by Ta0, before exiting self refresh mode.
2. Device must be in the all banks idle state prior to entering self refresh mode.
3. NOPs or DESELECTs is required for
4. AR = AUTO REFRESH.
5. CKE must remain LOW to remain in self refresh.
The self refresh mode can be used to retain data in the Mobile DDR SDRAM even if the
rest of the system is powered down. When in the self refresh mode, the Mobile DDR
SDRAM retains data without external clocking. The SELF REFRESH command is initi-
ated like an AUTO REFRESH command, except that CKE is disabled (LOW). All
command and address input signals except CKE are “Don’t Care” during SELF REFRESH.
See Figure 48 on page 78 for details on entering and exiting self refresh mode. During
SELF REFRESH, the device is refreshed as identified in the extended mode register (see
PASR section on page 45).
The procedure for exiting SELF REFRESH requires a sequence of commands. First, CK
must be stable prior to CKE going back HIGH. When CKE is HIGH, the Mobile DDR
SDRAM must have NOP commands issued for
already in progress.
During SELF REFRESH operation, refresh intervals are scheduled internally and may
vary. These intervals may be different than the specified
SELF REFRESH command must not be used as a substitute for the AUTO REFRESH
command.
2
t
IH
t
CH
t
CL
t
IS
AR
T1
Enter self refresh mode
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XSR time with at least two clock pulses.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x16, x32 Mobile DDR SDRAM
Ta0
1
t
CK
t
XSR to complete any internal refresh
t
NOP
IS
Ta1
t
Exit self refresh mode
REFI time. For this reason, the
t
XSR
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©2007 Micron Technology, Inc. All rights reserved.
3
Timing Diagrams
t
IS
Valid
Valid
Tb0
Don’t Care
t
IH
Preliminary