mt45w2mw16pga Micron Semiconductor Products, mt45w2mw16pga Datasheet - Page 6

• Manufacturer Part Number: mt45w2mw16pga
• Description: 32mb 2 Meg X 16 Async/page Cellularram 1.0 Memory
• Manufacturer: Micron Semiconductor Products

Ball Descriptions
Table 1:
PDF: 09005aef82832fa7 / Source: 09005aef82832f97
32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN
H6, G2, H1, D3,
G3, H5, H4, H3,
H2, D4, C4, C3,
B4, B3, A5, A4,
D2, C2, C1, B1,
E4, F4, F3, G4,
G1, F1, F2, E2,
G6, F6, F5, E5,
D5, C6, C5, B6
Assignment
VFBGA Ball
A3
B5
A1
A2
B2
G5
A6
D6
D1
E3
E1
E6
VFBGA Ball Descriptions
DQ[15:0]
Symbol
A[20:0]
V
V
WE#
OE#
UB#
CE#
LB#
ZZ#
V
V
NC
CC
SS
CC
SS
Q
Q
Output
Supply
Supply
Supply
Supply
Input/
Input
Input
Input
Input
Input
Input
Input
Type
Address inputs: Inputs for the address accessed during READ or WRITE operations.
The address lines are also used to define the value to be loaded into the CR.
Chip enable: Activates the device when LOW. When CE# is HIGH, the device is
disabled and goes into standby power mode.
Lower byte enable: DQ[7:0].
Output enable: Enables the output buffers when LOW. When OE# is HIGH, the
output buffers are disabled.
Upper byte enable: DQ[15:8].
Write enable: Enables WRITE operations when LOW.
Sleep enable: When ZZ# is LOW, the CR can be loaded or the device can enter one
of two low-power modes (DPD or PAR).
Data inputs/outputs.
Not internally connected.
Device power supply: (1.7–1.95V) Power supply for device core operation.
I/O power supply: (1.7–3.6V) Power supply for input/output buffers.
V
V
SS
SS
Q must be connected to ground.
must be connected to ground.
32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Description
©2007 Micron Technology, Inc. All rights reserved.
Ball Descriptions