pi7c8154a Pericom Semiconductor Corporation, pi7c8154a Datasheet - Page 32

• Manufacturer Part Number: pi7c8154a
• Description: 2-port Pci-to-pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

2.8.2
The configuration space is accessed by a Type 0 configuration transaction on the primary interface.
The configuration space cannot be accessed from the secondary bus. The PI7C8154A responds to a
Type 0 configuration transaction by asserting P_DEVSEL# when the following conditions are met
during the address phase:
!
!
!
PI7C8154A limits all configuration access to a single DWORD data transfer and returns target-
disconnect with the first data transfer if additional data phases are requested. Because read
transactions to configuration space do not have side effects, all bytes in the requested DWORD are
returned, regardless of the value of the byte enable bits.
Type 0 configuration write and read transactions do not use data buffers; that is, these transactions
are completed immediately, regardless of the state of the data buffers. The PI7C8154A ignores all
Type 0 transactions initiated on the secondary interface.
TYPE 1 TO TYPE 0 CONFIGURATION
Type 1 configuration transactions are used specifically for device configuration in a hierarchical
PCI bus system. A PCI-to-PCI bridge is the only type of device that should respond to a Type 1
configuration command. Type 1 configuration commands are used when the configuration access is
intended for a PCI device that resides on a PCI bus other than the one where the Type 1 transaction
is generated.
PI7C8154A performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on
the primary bus and is intended for a device attached directly to the secondary bus. PI7C8154A
must convert the configuration command to a Type 0 format so that the secondary bus device can
respond to it. Type 1 to Type 0 translations are performed only in the downstream direction; that is,
PI7C8154A generates a Type 0 transaction only on the secondary bus, and never on the primary
bus.
PI7C8154A responds to a Type 1 configuration transaction and translates it into a Type 0
transaction on the secondary bus when the following conditions are met during the address phase:
!
!
!
When PI7C8154A translates the Type 1 transaction to a Type 0 transaction on the secondary
interface, it performs the following translations to the address:
!
!
!
!
PI7C8154A asserts a unique address line based on the device number. These address lines may be
used as secondary bus IDSEL signals. The mapping of the address lines depends on the device
The bus command is a configuration read or configuration write transaction.
Lowest two address bits P_AD[1:0] must be 00b.
Signal P_IDSEL must be asserted.
The lowest two address bits on P_AD[1:0] are 01b.
The bus number in address field P_AD[23:16] is equal to the value in the secondary bus
number register in configuration space.
The bus command on P_CBE[3:0] is a configuration read or configuration write transaction.
Sets the lowest two address bits on S_AD[1:0] to 0.
Decodes the device number and drives the bit pattern specified in Table 2-6 on S_AD[31:16]
for the purpose of asserting the device’s IDSEL signal.
Sets S_AD[15:11] to 0.
Leaves unchanged the function number and register number fields.
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ASYNCHRONOUS 2-PORT
JULY 2004 REVISION 1.00
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A